Patents by Inventor Ishan Khera

Ishan Khera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240221820
    Abstract: A memory circuit includes a global control circuit, a first local control circuit and a first set of word line post-decoder circuits. The global control circuit is configured to generate a first and second set of global pre-decoder signals and a first set of local address signals. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and a second set of local pre-decoder signals in response to the second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals. The first set of word line post-decoder circuits is configured to generate a first set of word line signals.
    Type: Application
    Filed: March 11, 2024
    Publication date: July 4, 2024
    Inventors: Sanjeev Kumar JAIN, Ishan KHERA, Atul KATOCH
  • Patent number: 11929110
    Abstract: A memory circuit includes a global control circuit, a first local control circuit, and a first set of word line post-decoder circuits coupled to a first set of memory cells that is configured to store a first set of data. The global control circuit is configured to generate a first and second set of global pre-decoder signals, and a first set of local address signals. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first and second set of local pre-decoder signals in response to the corresponding first and second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals in response to the first set of local address signals and the first clock signal.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sanjeev Kumar Jain, Ishan Khera, Atul Katoch
  • Publication number: 20240055032
    Abstract: Systems and methods are provided for a memory device including a first memory array, a local input/output (LIO) circuit, and a global input/output (GIO) circuit. The first memory array includes a memory cell and a local bit line. The LIO circuit is configured to receive a local bit line signal on the local bit line and to generate a global bit line signal on a global bit line based on the local bit line signal. The GIO circuit is coupled to the LIO circuit and is configured to receive the global bit line signal. The GIO circuit comprises a latch circuit including a global bit line signal latch that is configured to latch the global bit line signal, and a booster circuit that is configured to drive the global bit line signal in the GIO circuit based on a previous global bit line signal.
    Type: Application
    Filed: July 13, 2023
    Publication date: February 15, 2024
    Inventors: Ishan Khera, Atul Katoch
  • Publication number: 20230170010
    Abstract: A memory circuit includes a global control circuit, a first local control circuit, and a first set of word line post-decoder circuits coupled to a first set of memory cells that is configured to store a first set of data. The global control circuit is configured to generate a first and second set of global pre-decoder signals, and a first set of local address signals. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first and second set of local pre-decoder signals in response to the corresponding first and second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals in response to the first set of local address signals and the first clock signal.
    Type: Application
    Filed: May 17, 2022
    Publication date: June 1, 2023
    Inventors: Sanjeev Kumar JAIN, Ishan KHERA, Atul KATOCH
  • Patent number: 10861534
    Abstract: The claimed subject matter relate to circuits and/or methods, which operate to introduce a variable delay in a write-assist signal to a write driver of an array of SRAM cells. Particularly, a variable delay may be introduced by way of a voltage tracking circuit, which may generate a trigger signal in response to a voltage signal from an array of access devices that replicate access devices of the array of SRAM cells.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: December 8, 2020
    Assignee: Arm Limited
    Inventors: Ankur Goel, Ishan Khera, Nimish Sharma, Ishita Satishchandra Desai, Vikash Kumar, Nitesh Gautam
  • Publication number: 20200312403
    Abstract: Briefly, embodiments of claimed subject matter relate to circuits and/or methods, which operate to introduce a variable delay in a write-assist signal to a write driver of an array of SRAM cells. In particular embodiments, a variable delay may be introduced by way of a voltage tracking circuit, which may generate a trigger signal in response to a voltage signal from an array of access devices that replicate access devices of the array of SRAM cells.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Ankur Goel, Ishan Khera, Nimish Sharma, Ishita Satishchandra Desai, Vikash Kumar, Nitesh Gautam