Patents by Inventor Ishtiaq Ahsan
Ishtiaq Ahsan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150294738Abstract: A tristate inverter array test structure and method of testing structures in a microchip are disclosed. The structure includes: a PFET stack in series with an NFET stack; an inverted wordline driving a PFET of the PFET stack; a worldline driving an NFET of the NFET stack; a data_in line connecting to an input of the PFET stack and the NFET stack; and a data_out line connecting to an output of the PFET stack and the NFET stack.Type: ApplicationFiled: April 15, 2014Publication date: October 15, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ishtiaq AHSAN, Fred J. TOWLER, Robert C. WONG
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Patent number: 8610451Abstract: A test structure for testing transistor gate structures in an IC device includes one or more probe pads formed at an active area of the IC device; one or more first conductive lines formed at the active area of the IC device, in electrical contact with the one or more probe pads; one or more second conductive lines formed at a gate conductor level of the IC device, in electrical contact with the one or more first conductive lines; and a gate electrode structure to be tested in electrical contact with the one or more second conductive lines; wherein the electrical contact between the one or more second conductive lines and the one or more first conductive lines is facilitated by a localized dielectric breakdown of a gate dielectric material disposed between the one or more second conductive lines and the one or more first conductive lines.Type: GrantFiled: November 16, 2010Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: Ishtiaq Ahsan, David M. Fried, Lidor Goren, Jiun-Hsin Liao
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Publication number: 20120119778Abstract: A test structure for testing transistor gate structures in an IC device includes one or more probe pads formed at an active area of the IC device; one or more first conductive lines formed at the active area of the IC device, in electrical contact with the one or more probe pads; one or more second conductive lines formed at a gate conductor level of the IC device, in electrical contact with the one or more first conductive lines; and a gate electrode structure to be tested in electrical contact with the one or more second conductive lines; wherein the electrical contact between the one or more second conductive lines and the one or more first conductive lines is facilitated by a localized dielectric breakdown of a gate dielectric material disposed between the one or more second conductive lines and the one or more first conductive lines.Type: ApplicationFiled: November 16, 2010Publication date: May 17, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ishtiaq Ahsan, David M. Fried, Lidor Goren, Jiun-Hsin Liao
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Patent number: 8039837Abstract: A semiconductor test structure includes a PFET transistor, having a source region, a drain region, a gate disposed between the source region and the drain region, a body disposed under the gate, and a body contact. The source region and drain region float, and the body contact is electrically connected to the body of the PFET transistor and to the ground. This grounds the body of the PFET transistor, and the body contact of the test structure is electrically connected to a capacitor that is electrically connected to ground.Type: GrantFiled: May 26, 2009Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Oliver D. Patterson, Ishtiaq Ahsan
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Publication number: 20100301331Abstract: Test structures for in-line voltage contrast detection of PFET silicide encroachment defects are disclosed. Embodiments of the present invention provide for improved PFET test structures for detecting encroachment defects using VC imaging techniques. The test structures use body contacts, and the PFET components (source, drain, body, and gate) are either grounded, or floating, depending on the configuration. Some embodiments of the present invention also enable the use of positive mode conditions with PFET test structures, which provides for improved contrast in the VC images, improving the effectiveness of the defect detection achieved with VC imaging.Type: ApplicationFiled: May 26, 2009Publication date: December 2, 2010Applicant: International Business Machines CorporationInventors: Oliver D. Patterson, Ishtiaq Ahsan
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Patent number: 7781239Abstract: A semiconductor defect type determination method and structure. The method includes providing a semiconductor wafer comprising a first field effect transistor (FET) comprising a first type of structure and a second FET comprising a second different type of structure. A first procedure is performed to determine if a first current flow exists between a first conductive layer formed on the first FET and a second conductive layer formed on the first FET. A second procedure is performed to determine if a second current flow exists between a third conductive layer formed the second FET and a fourth conductive layer formed on the second FET. A determination is made from combining results of the first procedure and results of the second procedure that the first FET and the second FET each comprise a specified type of defect.Type: GrantFiled: January 10, 2008Date of Patent: August 24, 2010Assignee: International Business Machines CorporationInventors: Ishtiaq Ahsan, Andrew Alexander McKnight, Katsunori Onishi, Keith Howard Tabakman
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Patent number: 7733109Abstract: A test structure for resistive open detection using voltage contrast (VC) inspection and method for using such structure are disclosed. The test structure may include a comparator within the IC chip for comparing a resistance value of a resistive element under test to a reference resistance and outputting a result of the comparing that indicates whether the resistive open exists in the resistive element under test, wherein the result is detectable by the voltage contrast inspection.Type: GrantFiled: October 15, 2007Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: Ishtiaq Ahsan, Mark B. Ketchen, Kevin McStay, Oliver D. Patterson
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Patent number: 7719005Abstract: According to the present invention, there is disclosed a thermal detection device and method of using the device for characterizing and monitoring the dependence of pattern density on thermal absorption of a semiconductor. One or more of the devices can be disposed on a die of a test wafer. The thermal detection device comprises a silicon substrate having a test structure located substantially in the center of the silicon substrate. Frame shaped structures of polysilicon, silicon and oxide, in various configurations, form a collocated arrangement on the silicon substrate. The test wafer is subjected to a rapid thermal process and the resistance of the at least one testing structure is measured and the measured resistance of the at least one test structure is tabulated to a thermal absorption value of the at least one die.Type: GrantFiled: February 7, 2007Date of Patent: May 18, 2010Assignee: International Buriness Machines CorporationInventors: Ishtiaq Ahsan, Oleg Gluschenkov
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Patent number: 7612371Abstract: The present invention addresses detection of charge-induced defects through test structures that can be easily incorporated on a wafer to detect charge-induced damage in the back-end-of-line processing of a semiconductor processing line. A test macro is designed to induce an arc from a charge accumulating antenna structure to another charge accumulating antenna structure across parallel plate electrodes. When an arc of a predetermined sufficient strength is present, the macro will experience a voltage breakdown that is measurable as a short. The parallel plate electrodes may both be at the floating potential of the microchip to monitor CMP-induced or lithographic-induced charge failure mechanisms, or have one electrode electrically connected to a ground potential structure to capture charge induced damage, hence having the capability to differentiate between the two.Type: GrantFiled: January 17, 2006Date of Patent: November 3, 2009Assignee: International Business Machines CorporationInventors: Ishtiaq Ahsan, Christine M. Bunke, Stephen E. Greco
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Publication number: 20090179661Abstract: A semiconductor defect type determination method and structure. The method includes providing a semiconductor wafer comprising a first field effect transistor (FET) comprising a first type of structure and a second FET comprising a second different type of structure. A first procedure is performed to determine if a first current flow exists between a first conductive layer formed on the first FET and a second conductive layer formed on the first FET. A second procedure is performed to determine if a second current flow exists between a third conductive layer formed the second FET and a fourth conductive layer formed on the second FET. A determination is made from combining results of the first procedure and results of the second procedure that the first FET and the second FET each comprise a specified type of defect.Type: ApplicationFiled: January 10, 2008Publication date: July 16, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ishtiaq Ahsan, Andrew Alexander McKnight, Katsunori Onishi, Keith Howard Tabakman
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Publication number: 20090096461Abstract: A test structure for resistive open detection using voltage contrast (VC) inspection and method for using such structure are disclosed. The test structure may include a comparator within the IC chip for comparing a resistance value of a resistive element under test to a reference resistance and outputting a result of the comparing that indicates whether the resistive open exists in the resistive element under test, wherein the result is detectable by the voltage contrast inspection.Type: ApplicationFiled: October 15, 2007Publication date: April 16, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ishtiaq Ahsan, Mark B. Ketchen, Kevin McStay, Oliver D. Patterson
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Patent number: 7515502Abstract: A method for using photolithographic dummy memory cells arranged in rings around a set of primary memory cells as test structures and as redundant memory cells. Also circuits and structures of memory arrays having multiple-use dummy memory cells.Type: GrantFiled: September 18, 2007Date of Patent: April 7, 2009Assignee: International Business Machines CorporationInventors: Ishtiaq Ahsan, Louis Lu-Chen Hsu, Xu Ouyang
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Publication number: 20090073796Abstract: A method for using photolithographic dummy memory cells arranged in rings around a set of primary memory cells as test structures and as redundant memory cells. Also circuits and structures of memory arrays having multiple-use dummy memory cells.Type: ApplicationFiled: September 18, 2007Publication date: March 19, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ishtiaq Ahsan, Louis Lu-Chen Hsu, Xu Ouyang
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Publication number: 20080185583Abstract: According to the present invention, there is disclosed a thermal detection device and method of using the device for characterizing and monitoring the dependence of pattern density on thermal absorption of a semiconductor. One or more of the devices can be disposed on a die of a test wafer. The thermal detection device comprises a silicon substrate having a test structure located substantially in the center of the silicon substrate. Frame shaped structures of polysilicon, silicon and oxide, in various configurations, form a collocated arrangement on the silicon substrate. The test wafer is subjected to a rapid thermal process and the resistance of the at least one testing structure is measured and the measured resistance of the at least one test structure is tabulated to a thermal absorption value of the at least one die.Type: ApplicationFiled: February 7, 2007Publication date: August 7, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: ISHTIAQ AHSAN, OLEG GLUSCHENKOV
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Patent number: 7408421Abstract: A device and method for determining a thermal absorption of a part of an integrated circuit (IC) are provided. A specially designed ring oscillator including a non-silicided poly-silicon resistor is used for the determination. The parameters of the ring oscillator are designed/tuned so that a delay of the ring oscillator varies predominantly with a variation in a resistance of the non-silicided poly-silicon resistor. The dimensions of the non-silicided poly-silicon resistor are large enough so that the resistance of the non-silicided poly-silicon resistor is immune to the small process variations of the poly-silicon length and width. The resistance of the non-silicided poly-silicon resistor varies with the thermal absorption of the part of the IC. As such, the thermal absorption of the part of the IC may be determined based on the delay of the ring oscillator.Type: GrantFiled: July 5, 2006Date of Patent: August 5, 2008Assignee: International Business Machines CorporationInventors: Ishtiaq Ahsan, Edward P. Maciejewski, Noah D. Zamdmer
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Patent number: 7396694Abstract: Detection of a profile drift of a polysilicon line is enhanced by a test structure that (1) measures a bottom width and an average width of a cross sectional area of the same polysilicon line (2) correlates the two measurements, and (3) compares such correlation with a previous correlation of bottom width to average width of cross sectional area of the same polysilicon line.Type: GrantFiled: October 6, 2006Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Ishtiaq Ahsan, Edward P. Maciejewski
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Publication number: 20080007354Abstract: A device and method for determining a thermal absorption of a part of an integrated circuit (IC) are provided. A specially designed ring oscillator including an un-silicided poly-silicon resistor is used for the determination. The parameters of the ring oscillator are designed/tuned so that a delay of the ring oscillator varies predominantly with a variation in a resistance of the un-silicided poly-silicon resistor. The dimensions of the un-silicided poly-silicon resistor are large enough so that the resistance of the un-silicided poly-silicon resistor is immune to the small process variations of the poly-silicon length and width. The resistance of the un-silicided poly-silicon resistor varies with the thermal absorption of the part of the IC. As such, the thermal absorption of the part of the IC may be determined based on the delay of the ring oscillator.Type: ApplicationFiled: July 5, 2006Publication date: January 10, 2008Inventors: Ishtiaq Ahsan, Edward P. Maciejewski, Noah D. Zamdmer
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Publication number: 20070164421Abstract: The present invention addresses detection of charge-induced defects through test structures that can be easily incorporated on a wafer to detect charge-induced damage in the back-end-of-line processing of a semiconductor processing line. A test macro is designed to induce an arc from a charge accumulating antenna structure to another charge accumulating antenna structure across parallel plate electrodes. When an arc of a predetermined sufficient strength is present, the macro will experience a voltage breakdown that is measurable as a short. The parallel plate electrodes may both be at the floating potential of the microchip to monitor CMP-induced or lithographic-induced charge failure mechanisms, or have one electrode electrically connected to a ground potential structure to capture charge induced damage, hence having the capability to differentiate between the two.Type: ApplicationFiled: January 17, 2006Publication date: July 19, 2007Applicant: International Business Machines CorporationInventors: Ishtiaq Ahsan, Christine Bunke, Stephen Greco
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Publication number: 20070087593Abstract: Detection of a profile drift of a polysilicon line is enhanced by a test structure that (1) measures a bottom width and an average width of a cross sectional area of the same polysilicon line (2) correlates the two measurements, and (3) compares such correlation with a previous correlation of bottom width to average width of cross sectional area of the same polysilicon line.Type: ApplicationFiled: October 6, 2006Publication date: April 19, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ishtiaq Ahsan, Edward Maciejewski
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Patent number: 7135346Abstract: Detection of a profile drift of a polysilicon line is enhanced by a test structure that (1) measures a bottom width and an average width of a cross sectional area of the same polysilicon line (2) correlates the two measurements, and (3) compares such correlation with a previous correlation of bottom width to average width of cross sectional area of the same polysilicon line.Type: GrantFiled: July 29, 2004Date of Patent: November 14, 2006Assignee: International Business Machines CorporationInventors: Ishtiaq Ahsan, Edward P. Maciejewski