Patents by Inventor Ishwar AGARWAL

Ishwar AGARWAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200409844
    Abstract: Disclosed embodiments relate to an asynchronous cache-flush engine to manage platform coherent and memory-side caches. In one example, a system includes multiple interconnected sockets each including a cache flush engine (CFE), a core, and an associated cache hierarchy including a plurality of caches, one of the CFEs designated as a master CFE in a master socket, the master CFE to: receive a request specifying an opcode and a range, the opcode calling for a cache flush, execute the request to cause writeback and, if indicated by the request, invalidation of modified cache lines in the master socket falling within the range, and communicate a request to any other, slave sockets in the system each having a slave CFE to cause writeback and, if indicated by the request, invalidation of modified cache lines in the slave socket falling within the range.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Inventors: Vivekananthan SANJEEPAN, Gideon GERZON, Ishwar AGARWAL, Rajesh SANKARAN, Andy RUDOFF
  • Publication number: 20200334179
    Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.
    Type: Application
    Filed: April 3, 2020
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Ishwar Agarwal, Peeyush Purohit, Nitish Paliwal, Archana Srinivasan
  • Publication number: 20200328879
    Abstract: An apparatus includes a port with circuitry to implement one or more layers of a Compute Express Link (CXL)-based protocol. The port includes an agent to obtain information to be transmitted to another device over a link based on the CXL-based protocol via a flit, encrypt at least a portion of the information to yield a ciphertext, generate a cyclic redundancy check (CRC) code based on the ciphertext, and cause a flit to be generated comprising the ciphertext. The port is to use the circuitry to transmit the flit and the CRC code to the other device over the link.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 15, 2020
    Applicant: Intel Corporation
    Inventors: Raghunandan Makaram, Ishwar Agarwal, Kirk S. Yap, Nitish Paliwal, David J. Harriman, Ioannis T. Schoinas
  • Patent number: 10776309
    Abstract: A hetero-mesh architecture is provided to enable varying densities of tile in a multi-core processor. The hetero-mesh architecture includes areas with different tile sizes and wire densities operating and different bandwidths. A split merge switch is utilized between the different parts of the hetero-mesh to enable the sending of packets from tiles in one area of the hetero-mesh to another area of the hetero-mesh while employing a single end to end communication protocol.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: September 15, 2020
    Assignee: INTEL CORPORATION
    Inventors: Rahul Pal, Ishwar Agarwal
  • Patent number: 10614000
    Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Ishwar Agarwal, Peeyush Purohit, Nitish Paliwal, Archana Srinivasan
  • Patent number: 10579551
    Abstract: Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Ishwar Agarwal, Omid Azizi, Chandan Egbert, Amin Firoozshahian, David Christopher Hansen, Andreas Kleen, Mahesh Maddury, Mahesh Madhav, Ashok Raj, Alexandre Solomatnikov, Stephen Van Doren
  • Publication number: 20200050570
    Abstract: In one embodiment, an apparatus comprises: an endpoint circuit to perform an endpoint operation on behalf of a host processor; and an input/output circuit coupled to the endpoint circuit to receive telemetry information from the endpoint circuit, encode the telemetry information into a virtual bus encoding, place the virtual bus encoding into a payload field of a control message, and communicate the control message having the payload field including the virtual bus encoding to an upstream device. Other embodiments are described and claimed.
    Type: Application
    Filed: October 22, 2019
    Publication date: February 13, 2020
    Inventors: Ishwar Agarwal, Nitish Paliwal
  • Publication number: 20200021540
    Abstract: In one embodiment, an input/output port includes a stateful transmit port having: a history storage to store a value corresponding to a transmit on change field of a prior data packet; a comparator to compare a transmit on change field of the data packet to the value stored in the history storage; and a selection circuit to output the data packet without the transmit on change field when the transmit on change field of the data packet matches the value. Other embodiments are described and claimed.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Pratik Marolia, Rajesh Sankaran, Ishwar Agarwal, Nitish Paliwal
  • Publication number: 20200012604
    Abstract: In one embodiment, a processor includes: one or more cores to execute instructions; at least one cache memory; and a coherence circuit coupled to the at least one cache memory. The coherence circuit may have a direct memory access circuit to receive a write request, and based at least in part on an address of the write request, to directly send the write request to a device coupled to the processor via a first bus, to cause the device to store data of the write request to a device-attached memory. Other embodiments are described and claimed.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Inventor: Ishwar Agarwal
  • Publication number: 20200004703
    Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.
    Type: Application
    Filed: September 10, 2019
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Rajesh M. Sankaran, David J. Harriman, Sean O. Stalley, Rupin H. Vakharwala, Ishwar Agarwal, Pratik M. Marolia, Stephen R. Van Doren
  • Patent number: 10437616
    Abstract: Aspects of the embodiments are directed to systems and methods performed by a virtual shared work queue (VSWQ). The VSWQ can receive an enqueue command (ENQCMD/S) destined for a shared work queue of a peripheral device. The VSWQ can determine a value of a credit counter for the shared work queue, wherein a credit of the credit counter represents an availability of the shared work queue to accept the enqueue command. The VSWQ can respond to the enqueue command based on the value of the credit counter.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Ishwar Agarwal, Rajesh Sankaran, Stephen Van Doren
  • Publication number: 20190278721
    Abstract: In one embodiment, an apparatus includes: a first memory controller to control access to a first memory, the first memory controller including a memory mirroring circuit, in response to a memory write request from a first processor socket for which the first memory comprises a primary memory region, to cause data associated with the memory write request to be written to the first memory and to send a shadow memory write request to a second memory to cause the second memory to write the data into a secondary memory region; and a shadow memory table including a plurality of entries each to store an association between a primary memory region and a secondary memory region. The memory mirroring circuit may access the shadow memory table to identify the secondary memory region. Other embodiments are described and claimed.
    Type: Application
    Filed: May 29, 2019
    Publication date: September 12, 2019
    Inventors: Ishwar Agarwal, Theodros Yigzaw
  • Publication number: 20190196988
    Abstract: Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.
    Type: Application
    Filed: December 27, 2017
    Publication date: June 27, 2019
    Inventors: Ishwar Agarwal, Omid Azizi, Chandan Egbert, Amin Firoozshahian, David Christopher Hansen, Andreas Kleen, Mahesh Maddury, Mahesh Madhav, Ashok Raj, Alexandre Solomatnikov, Stephen Van Doren
  • Publication number: 20190102326
    Abstract: Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.
    Type: Application
    Filed: September 30, 2017
    Publication date: April 4, 2019
    Inventors: Ishwar Agarwal, Rupin H. Vakharwala, Rajesh M. Sankaran, Stephen R. Van Doren
  • Publication number: 20190102292
    Abstract: There is disclosed in an example a peripheral component interconnect express (PCIe) controller to provide coherent memory mapping between an accelerator memory and a host memory address space, having: a PCIe controller hub including extensions to provide a coherent accelerator interconnect (CAI) to provide bias-based coherency tracking between the accelerator memory and the host memory address space; wherein the extensions include: a mapping engine to provide opcode mapping between PCIe instructions and on-chip system fabric (OSF) instructions for the CAI; and a tunneling engine to provide scalable memory interconnect (SMI) tunneling of host memory operations to the accelerator memory via the CAI.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Ishwar Agarwal, Stephen R. Van Doren, Ramacharan Sundararaman
  • Publication number: 20190095363
    Abstract: Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 28, 2019
    Applicant: Intel Corporation
    Inventors: Ishwar Agarwal, Peeyush Purohit, Nitish Paliwal, Archana Srinivasan
  • Publication number: 20190042455
    Abstract: Systems, methods, and devices can include ports comprising hardware to support the multilane link, wherein the multi-lane link comprises a first set of bundled lanes configured in a first direction and a second set of bundled lanes configured in a second direction, the second direction is opposite to the first direction, the first set of bundled lanes comprises an equal number of lanes as the second set of bundled lanes. An input/output (I/O) bridge logic implemented at least partially in hardware can receive across the multilane link an cache invalidation request received on a port compliant with an I/O protocol. A memory controller logic implemented at least partially in hardware can invalidate a cache line based on receiving the cache invalidation request on the I/O protocol. The memory controller can transmit across the multilane link a memory invalidation response message on a port compliant with a device-attached memory access protocol.
    Type: Application
    Filed: September 19, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Ishwar Agarwal, Rajesh M. Sankaran, Stephen R. Van Doren
  • Publication number: 20190042430
    Abstract: Techniques and apparatus to manage cache coherency for different types of cache memory are described. In one embodiment, an apparatus may include at least one processor, at least one cache memory, and logic, at least a portion comprised in hardware, the logic to receive a memory operation request associated with the at least one cache memory, determine a cache status of the memory operation request, the cache status indicating one of a giant cache status or a small cache status, perform the memory operation request via a small cache coherence process responsive to the cache status being a small cache status, and perform the memory operation request via a giant cache coherence process responsive to the cache status being a small cache status. Other embodiments are described and claimed.
    Type: Application
    Filed: August 7, 2017
    Publication date: February 7, 2019
    Inventors: RAJESH SANKARAN, ISHWAR AGARWAL, STEPHEN VAN DOREN
  • Publication number: 20190004990
    Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to detect a message to communicate via an interconnect coupled with a device capable of communication via a plurality of interconnect protocols, the plurality of interconnect protocols comprising a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol. Embodiments also include determining an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message, and providing the message to a multi-protocol multiplexer coupled with the interconnect, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device.
    Type: Application
    Filed: July 1, 2017
    Publication date: January 3, 2019
    Inventors: STEPHEN R. VAN DOREN, RAJESH M. SANKARAN, DAVID A. KOUFATY, RAMACHARAN SUNDARARAMAN, ISHWAR AGARWAL
  • Publication number: 20180189104
    Abstract: Aspects of the embodiments are directed to systems and methods performed by a virtual shared work queue (VSWQ). The VSWQ can receive an enqueue command (ENQCMD/S) destined for a shared work queue of a peripheral device. The VSWQ can determine a value of a credit counter for the shared work queue, wherein a credit of the credit counter represents an availability of the shared work queue to accept the enqueue command. The VSWQ can respond to the enqueue command based on the value of the credit counter.
    Type: Application
    Filed: December 31, 2016
    Publication date: July 5, 2018
    Applicant: Intel Corporation
    Inventors: Ishwar Agarwal, Rajesh Sankaran, Stephen Van Doren