Abstract: A programmable semiconductor device and a method of manufacturing the same. The device includes: (1) a substrate composed at least in part of silicon, (2) a dielectric layer located over the substrate and (3) a control gate located over the dielectric layer wherein the dielectric layer contains a substantial concentration of an isotope of hydrogen.

Abstract: The present invention provides a process for fabricating merged integrated circuits on a semiconductor wafer substrate. The process comprises forming a gate oxide on the semiconductor wafer substrate, forming a first transistor having a first gate on the gate oxide, and forming a second transistor having a second gate on the same gate oxide. The first transistor is optimized to a first operating voltage by varying a physical property of the first gate, varying a first tub doping profile, or varying a first source/drain doping profile. The second transistor is optimized to a second operating voltage by varying a physical property of the second gate, varying a second tub doping profile, or varying a second source/drain doping profile of the second transistor. These physical characteristics may be changed in any combination or singly to achieve the determined optimization of the operating voltage of any given transistor.

Abstract: A method of forming a multi-layered dual-doped polysilicon structure that minimizes Boron penetration into the n+ polysilicon during formation of the p+ polysilicon. The method of the present invention also reduces the migration of Boron (p+ gate dopant) from the p+ polysilicon and the migration of Arsenic and/or Phosphorous (n+ gate dopant) from the n+ polysilicon during subsequent fabrication processing steps. The present invention is also directed to a semiconductor device having a gate dopant barrier that minimizes gate dopant penetration and migration.

Abstract: The present invention provides methods of manufacturing a field oxide isolation structure over a semiconductor. One of the methods includes the steps of: (1) depositing a first stack-nitride sublayer over the semiconductor at a first deposition rate and (2) subsequently depositing a second stack-nitride sublayer over the first stack-sublayer at a second deposition rate that is either greater or less than the first deposition rate. The first and second deposition rates provide first and second stack-nitride sublayers that cooperate to form a relatively thin, uniform thickness of the field oxide isolation structure over the semiconductor and provide a stress-accommodating system within the semiconductor. The varying rates of deposition and accompanying changes in mixture ratio, produce a stack that is better able to absorb stress, has greater uniformity and is far less subject to the disadvantageous phenomenon of stack-lifting, particularly encountered in semiconductor having a PADOX layer deposited thereon.

Abstract: The present invention provides, in one embodiment, a method of fabricating a heterostructure bipolar transistor. This particular embodiment comprises forming a n-type doped region in a semiconductor substrate to form a collector, epitaxially forming a base on the collector, epitaxially doping the base with indium while forming the base, and forming an emitter on the base. The base is epitaxially formed, and at the same time the base is doped with indium. In other words, the indium is epitaxially incorporated within the base as the base is being formed. In addition to the indium, the base may also be epitaxially doped with boron. Since, indium is incorporated into the base with the same epitaxial process used to form the base, the damage typically associated with conventional implantation processes are not present, and thus, the high annealing temperatures to repair the damage are not required. The base can be doped and formed at the same time; thereby, saving processing time.

Abstract: This invention includes a novel synthesis of a three-step process of growing, depositing and growing SiO.sub.2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer, which contains a substantial concentration of a hydrogen isotope, such as deuterium, forms an interface with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated SiO.sub.2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO.sub.2 interface. The entire synthesis is done under low-pressure (e.g., 0.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device. The device includes: (1) a substrate composed at least in part of silicon and (2) a film located over the substrate and having a substantial concentration of an isotope of hydrogen located in the film.

Abstract: The specification describes intergate dielectrics between the floating silicon gate and the control silicon gate in MOS memory devices. The intergate dielectrics are composite structures of SiO.sub.2 --Ta.sub.2 O.sub.5 --SiO.sub.2 with the first SiO.sub.2 layer grown on the floating gate,, and all layers preferably produced in situ in an LPCVD reactor. After formation of the composite SiO.sub.2 --Ta.sub.2 O.sub.5 --SiO.sub.2 dielectric, it is annealed at low pressure to densify the SiO.sub.2 layers. Electrical measurements show that the charge trap density in the intergate dielectric is substantially lower than in layered dielectrics produced by prior techniques.

Abstract: The present invention provides a method of forming an alloy interconnect in an integrated circuit having a dielectric layer with an opening formed therein. In an advantageous embodiment, the method comprises the steps of forming a metal alloy within the opening. The metal alloy comprises at least a first and a second metal with the first metal selected from a Group 13 metal and having a melting point substantially lower than a melting point of the second metal and the dielectric. This particular method further comprises the steps of subjecting the first and second metals to a temperature sufficient to melt the first metal and reflow the metal alloy.

Abstract: A bipolar transistor and a method of manufacturing the transistor. The transistor includes: (1) a substrate having a base region, an emitter region and a base-emitter junction between said base and emitter regions and (2) a substantial concentration of an isotope of hydrogen located in said biploar transistor.

Abstract: Indium is employed as the shallow portion of a lightly doped drain transistor.

Abstract: Sub-micron PMOSFETs including n.sup.+ polysilicon gates and buried channels having impurity concentrations comprising indium or gallium are provided. The buried channel PMOSFETs have improved short channel characteristics and are particularly suitable for use in CMOS technologies.

Abstract: Sub-micron PMOSFETs including n.sup.+ polysilicon gates and buried channels having impurity concentrations comprising indium or gallium are provided. The buried channel PMOSFETs have improved short channel characteristics and are particularly suitable for use in CMOS technologies.

Abstract: Indium doping is used to make bases of bipolar transistors with superior operational characteristics.