Abstract: A decision feedback equalizer system is disclosed. The decision feedback equalizer system includes a current summer core that in current mode, removes inter-symbol interference from a signal, and, a CMOS latch component, that is coupled to the current summer core, that receives a current mode signal and outputs a CMOS compatible signal. The components of the decision feedback equalizer system are controlled by a single clock.

Abstract: A decision feedback equalizer system is disclosed. The decision feedback equalizer system includes a current summer core that in current mode, removes inter-symbol interference from a signal, and, a CMOS latch component, that is coupled to the current summer core, that receives a current mode signal and outputs a CMOS compatible signal. The components of the decision feedback equalizer system are controlled by a single clock.

Abstract: A receiver (22) includes an IF filter (44) and a nearby process-variant circuit (80) formed on a common semiconductor substrate (24). The actual center frequency of the IF filter (44) is determined by resistors (70, 74) and capacitors (72, 76) exhibiting imprecise values and is unlikely to equal a nominal center frequency. The process-variant circuit (80) includes a test resistor (102) and test capacitor (104) formed using the same resistor-forming and capacitor-forming processes used to form the IF filter resistors (70, 74) and capacitors (72, 76). In response a test signal (88) from the process-variant circuit (80) and a reference signal (84) from a process-invariant circuit (82), a tuning parameter for a tunable local oscillator (90) is determined so that a local oscillation signal (94) will exhibit a frequency which, when mixed with an RF signal (38) yields an IF signal (42) at the actual center frequency of the IF filter (44).

Abstract: A receiver (22) includes an IF filter (44) and a nearby process-variant circuit (80) formed on a common semiconductor substrate (24). The actual center frequency of the IF filter (44) is determined by resistors (70, 74) and capacitors (72, 76) exhibiting imprecise values and is unlikely to equal a nominal center frequency. The process-variant circuit (80) includes a test resistor (102) and test capacitor (104) formed using the same resistor-forming and capacitor-forming processes used to form the IF filter resistors (70, 74) and capacitors (72, 76). In response a test signal (88) from the process-variant circuit (80) and a reference signal (84) from a process-invariant circuit (82), a tuning parameter for a tunable local oscillator (90) is determined so that a local oscillation signal (94) will exhibit a frequency which, when mixed with an RF signal (38) yields an IF signal (42) at the actual center frequency of the IF filter (44).

Abstract: An adaptive output driver includes circuitry for sensing the capacitive loading of a driver circuit and then adjusting the drive output so that the output signal possess a desired slew rate. In one embodiment, the circuit of the present invention includes a capacitance sensor, a control circuit, and an output driver. The capacitance sensor measures the unknown load capacitance. The control circuit generates a control signal in response to the capacitive load measurement. The output driver receives the control signal and in response produces an output level which when supplied to the capacitive load produces an output signal having the desired slew rate.

Abstract: A current-controlled output buffer circuit includes a control circuit, a charging circuit, and a discharging circuit. The control circuit is configured to receive a control signal, and in response produces a charging signal and a discharging signal. The charging circuit is configured to receive the charging signal and in response, supplies a charging current to an output terminal, the magnitude of said charging current producing a signal rise time. The discharging circuit is configured to receive the discharging signal and in response, sinks a discharging current from the output terminal, the magnitude of the discharging current producing a signal fall time.

Abstract: The present invention provides a digital-to-analog converter which uses two separate digital-to-analog converters for the first N-bits. The N+1 bit, which is the sign bit in a sign and magnitude digital format, is used to provide the difference between the two digital-to-analog converters to the output for a first value, and to switch the DAC outputs for a second value of the sign bit. The present invention thus eliminates the parasitic capacitance of the N+1 bit by using a differential input which is switched depending on the sign bit.

Abstract: A dual stage adaptive peak detect circuit includes a fast peak detector that detects the trends in the magnitude of the incoming signal and an adaptable peak detector that accurately follows the peak of the signal. A difference circuit detects the voltage difference between the outputs of the fast peak detector and the adaptable peak detector. A voltage-to-current converter feeds back the current-converted difference voltage to the adaptable peak detector to adjust its peak detection charge current. The dual stage adaptive peak detector of the present invention is thus capable of accurately following the peak of an incoming signal with varying amplitudes.

Abstract: A transmission line driver circuit for use in data communication transmitters that is capable of meeting the return loss specifications as well as the electrical interface specifications as defined by C.C.I.T.T. standards for E1/T1 transmission. The line driver circuit of the present invention maintains minimum output impedance during the entire dynamic range of the transmit signal while meeting the pulse shape template requirements. The circuit includes a predriver stage that controls the slew rate of the transmit signal within the constraints of the pulse template. This allows a subsequent output driver stage to enjoy fast slew rates, large gain and dynamic range, and very small output impedance to meet the return loss specification.