Abstract: An integrated circuit comprises an input node operable to receive test data. First circuitry configurable as a first delay circuit is coupled to the node, operable to generate a first test signal by delaying the test data a first delay time and operable to generate a second test signal by delaying the test data a second delay time. Second circuitry configurable as a first scan chain is coupled to the first delay circuit and is operable to receive the first test signal. Third circuitry configurable as a second scan chain is coupled to the first delay circuit and is operable to receive the second test signal.