Abstract: A wafer-scale integrated circuit wherein a plurality of memory cells on a wafer are connectable from a port to form a chain memory looping away from and back to the port by means of a serial connection of forward moving data registers and a serial connection of backward moving data registers between cells, has a reduced risk of any individual, otherwise functional cell being non-functional as a result of a failure elsewhere on the wafer of an associated global signal line by achieving a reduction in the numbers of global lines by providing the clock signal for controlling the shifting of data in the registers between the cells in parallel with the data, the inter-cell clock operating a multiple clock pulse generator in each cell.