Patents by Inventor Isoroku Ono
Isoroku Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8283252Abstract: A method of manufacturing a semiconductor wafer, including a step of differentiating the glossiness of a front surface from that of a rear surface of the wafer by holding the semiconductor wafer in a wafer holding hole formed in a carrier plate, and simultaneously polishing a front and back surface of said semiconductor wafer by driving said carrier plate to make a circular motion associated with no rotation on its own axis within a plane parallel with a surface of said carrier plate between a pair of polishing members disposed to face to each other, by using an abrasive body with a semiconductor wafer sink rate different in polishing from that of an abrasive body for one of a polishing member on an upper surface plate and a polishing member on a lower surface plate so as to simultaneously polish both the front and rear surfaces of the semiconductor wafer, or differentiating by differentiating the rotating speed of the upper surface plate from that of the lower surface plate.Type: GrantFiled: September 14, 2009Date of Patent: October 9, 2012Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toru Taniguchi, Etsuro Morita, Satoshi Matagawa, Seiji Harada, Isoroku Ono, Mitsuhiro Endo, Fumihiko Yoshida
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Patent number: 7951716Abstract: A wafer is produced at a step of polishing a predetermined face of a wafer to flatten the predetermined face while supplying a polishing liquid onto a bonded abrasive cloth, wherein the bonded abrasive cloth comprises a urethane bonding material consisting of a soft segment having a polyfunctional isocyanate and a hard segment having a polyfunctional polyol and having an expansion ratio of 1.1-4 times and silica having an average particle size of 0.2-10 ?m and a hydroxy group, and has a given ratio of the hard segment occupied in the urethane bonding material, a given volume ratio of silica and a given Shore D hardness.Type: GrantFiled: February 16, 2007Date of Patent: May 31, 2011Assignee: Sumco CorporationInventors: Etsurou Morita, Kazuo Hujie, Isoroku Ono
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Patent number: 7855129Abstract: A direct bonded SOI wafer having an entire buried oxide film layer covered and not exposed is manufactured by: (A) forming a laminated body by laminating a semiconductor wafer and a support wafer via an oxide film; and (B) forming a thin-film single crystal silicon layer on the support wafer using a buried oxide film layer by film-thinning the semiconductor wafer to a predetermined thickness. In a process (C) the entire buried oxide film layer is covered by a main surface on the laminating side of the support wafer and the single crystal silicon layer. The covering of the entire buried film layer is carried out by, between process (A) and (B), removing the oxide film formed on the circumferential end edge of the main surface on the laminating side and the chamfered portion to leave the oxide film only on the laminated surface except the circumferential end edge.Type: GrantFiled: May 12, 2010Date of Patent: December 21, 2010Assignee: Sumco CorporationInventors: Etsurou Morita, Shinji Okawa, Isoroku Ono
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Patent number: 7829436Abstract: A processing time required for regeneration of a layer transferred wafer is reduced and the regeneration cost is lowered, while a removal amount at the regeneration is decreased the number of regeneration times is increased. A main surface of a semiconductor wafer (13) has a main flat portion (13d) and a chamfered portion (13c) formed in the periphery of the main flat portion (13d), an ion implanted area (13b) is formed by implanting ions only into the main flat portion (13d), a laminated body (16) is formed by laminating the main flat portion (13d) on a main surface of a support wafer (14), and moreover, the semiconductor wafer (13) is separated from a thin layer (17) in the ion implanted area (13b) by heat treatment at a predetermined temperature so as to obtain a thick layer transferred wafer (12), which is to be regenerated.Type: GrantFiled: December 21, 2006Date of Patent: November 9, 2010Assignee: SUMCO CorporationInventors: Etsurou Morita, Shinji Okawa, Isoroku Ono
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Publication number: 20100219500Abstract: A direct bonded SOI wafer having an entire buried oxide film layer covered and not exposed is manufactured by: (A) forming a laminated body by laminating a semiconductor wafer and a support wafer via an oxide film; and (B) forming a thin-film single crystal silicon layer on the support wafer using a buried oxide film layer by film-thinning the semiconductor wafer to a predetermined thickness. In a process (C) the entire buried oxide film layer is covered by a main surface on the laminating side of the support wafer and the single crystal silicon layer. The covering of the entire buried film layer is carried out by, between process (A) and (B), removing the oxide film formed on the circumferential end edge of the main surface on the laminating side and the chamfered portion to leave the oxide film only on the laminated surface except the circumferential end edge.Type: ApplicationFiled: May 12, 2010Publication date: September 2, 2010Applicant: SUMCO CORPORATIONInventors: Etsurou MORITA, Shinji Okawa, Isoroku Ono
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Patent number: 7781309Abstract: A direct bonded SOI wafer having an entire buried oxide film layer covered and not exposed is manufactured by: (A) forming a laminated body by laminating a semiconductor wafer and a support wafer via an oxide film; and (B) forming a thin-film single crystal silicon layer on the support wafer using a buried oxide film layer by film-thinning the semiconductor wafer to a predetermined thickness. In a process (C) the entire buried oxide film layer is covered by a main surface on the laminating side of the support wafer and the single crystal silicon layer. The covering of the entire buried film layer is carried out by, between process (A) and (B), removing the oxide film formed on the circumferential end edge of the main surface on the laminating side and the chamfered portion to leave the oxide film only on the laminated surface except the circumferential end edge.Type: GrantFiled: December 21, 2006Date of Patent: August 24, 2010Assignee: Sumco CorporationInventors: Etsurou Morita, Shinji Okawa, Isoroku Ono
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Patent number: 7718507Abstract: A bonded wafer is produced by bonding an ion-implanted wafer for an active layer onto a wafer for a supporting substrate, and thereafter exfoliating the wafer for the active layer at the ion-implanted position through a heat treatment and then polishing a terrace portion of the resulting active layer with a predetermined fixed grain abrasive cloth to remove island-shaped projections on the terrace portion while controlling a scattering of terrace width and smoothness of an outer peripheral face of the active layer.Type: GrantFiled: March 8, 2007Date of Patent: May 18, 2010Assignee: Sumco CorporationInventors: Etsurou Morita, Kazuo Hujie, Isoroku Ono
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Patent number: 7713842Abstract: In a method for producing a bonded wafer by bonding a wafer for active layer to wafer for support layer and then thinning the wafer for active layer, a terrace grinding for forming a terrace portion is carried out prior to a step of exposing the oxygen ion implanted layer to thereby leave an oxide film on a terrace portion of the wafer for support layer.Type: GrantFiled: September 29, 2008Date of Patent: May 11, 2010Assignee: Sumco CorporationInventors: Hideki Nishihata, Isoroku Ono, Akihiko Endo
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Publication number: 20100009605Abstract: A method of manufacturing a semiconductor wafer, including a step of differentiating the glossiness of a front surface from that of a rear surface of the wafer by holding the semiconductor wafer in a wafer holding hole formed in a carrier plate, and simultaneously polishing a front and back surface of said semiconductor wafer by driving said carrier plate to make a circular motion associated with no rotation on its own axis within a plane parallel with a surface of said carrier plate between a pair of polishing members disposed to face to each other, by using an abrasive body with a semiconductor wafer sink rate different in polishing from that of an abrasive body for one of a polishing member on an upper surface plate and a polishing member on a lower surface plate so as to simultaneously polish both the front and rear surfaces of the semiconductor wafer, or differentiating by differentiating the rotating speed of the upper surface plate from that of the lower surface plate.Type: ApplicationFiled: September 14, 2009Publication date: January 14, 2010Inventors: Toru Taniguchi, Etsuro Morita, Satoshi Matagawa, Seiji Harada, Isoroku Ono, Mitsuhiro Endo, Fumihiko Yoshida
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Patent number: 7589023Abstract: A method of manufacturing a semiconductor wafer, comprising the step of differentiating the glossiness of a front surface from that of a rear surface of the wafer by using an abrasive cloth with a semiconductor wafer sink rate different in polishing from that of the other abrasive cloth for one of a polishing cloth (14) on an upper surface plate (12) and a polishing cloth (15) on a lower surface plate (13) so as to simultaneously polish both the front and rear surfaces of the semiconductor wafer (W), or differentiating by differentiating the rotating speed of the upper surface plate from that of the lower surface plate.Type: GrantFiled: April 23, 2001Date of Patent: September 15, 2009Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toru Taniguchi, Etsuro Morita, Satoshi Matagawa, Seiji Harada, Isoroku Ono, Mitsuhiro Endo, Fumihiko Yoshida
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Publication number: 20090098707Abstract: In a method for producing a bonded wafer by bonding a wafer for active layer to wafer for support layer and then thinning the wafer for active layer, a terrace grinding for forming a terrace portion is carried out prior to a step of exposing the oxygen ion implanted layer to thereby leave an oxide film on a terrace portion of the wafer for support layer.Type: ApplicationFiled: September 29, 2008Publication date: April 16, 2009Applicant: SUMCO CORPORATIONInventors: Hideki Nishihata, Isoroku Ono, Akihiko Endo
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Patent number: 7470169Abstract: During polishing of the semiconductor wafer by using a double-sided polisher, a larger difference as compared to the prior art is created between a frictional resistance acting on a front surface of a silicon wafer from an upper surface plate side and a frictional resistance acting on a back surface of the silicon wafer from a lower surface plate side. Thereby, respective wafers can be rotated at as 0.1 - 1.0 rpm within corresponding wafer holding holes. Accordingly, the rotation of the wafer would not be suspended even if there were any defective condition induced during polishing. Further, partial variation or deviation in polishing volume particular in the outer periphery of the wafer would be hard to occur. Therefore, the polish-sagging is suppressed and thus the improved degree of flatness of the wafer could be obtained.Type: GrantFiled: May 31, 2001Date of Patent: December 30, 2008Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toru Taniguchi, Isoroku Ono, Seiji Harada
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Publication number: 20070243694Abstract: A bonded wafer is produced by bonding an ion-implanted wafer for an active layer onto a wafer for a supporting substrate, and thereafter exfoliating the wafer for the active layer at the ion-implanted position through a heat treatment and then polishing a terrace portion of the resulting active layer with a predetermined fixed grain abrasive cloth to remove island-shaped projections on the terrace portion while controlling a scattering of terrace width and smoothness of an outer peripheral face of the active layer.Type: ApplicationFiled: March 8, 2007Publication date: October 18, 2007Inventors: Etsurou Morita, Kazuo Hujie, Isoroku Ono
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Publication number: 20070197035Abstract: A wafer is produced at a step of polishing a predetermined face of a wafer to flatten the predetermined face while supplying a polishing liquid onto a bonded abrasive cloth, wherein the bonded abrasive cloth comprises a urethane bonding material consisting of a soft segment having a polyfunctional isocyanate and a hard segment having a polyfunctional polyol and having an expansion ratio of 1.1-4 times and silica having an average particle size of 0.2-10 ?m and a hydroxy group, and has a given ratio of the hard segment occupied in the urethane bonding material, a given volume ratio of silica and a given Shore D hardness.Type: ApplicationFiled: February 16, 2007Publication date: August 23, 2007Applicant: SUMCO CORPORATIONInventors: Etsurou Morita, Kazuo Hujie, Isoroku Ono
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Publication number: 20070148914Abstract: A processing time required for regeneration of a layer transferred wafer is reduced and the regeneration cost is lowered, while a removal amount at the regeneration is decreased the number of regeneration times is increased. A main surface of a semiconductor wafer (13) has a main flat portion (13d) and a chamfered portion (13c) formed in the periphery of the main flat portion (13d), an ion implanted area (13b) is formed by implanting ions only into the main flat portion (13d), a laminated body (16) is formed by laminating the main flat portion (13d) on a main surface of a support wafer (14), and moreover, the semiconductor wafer (13) is separated from a thin layer (17) in the ion implanted area (13b) by heat treatment at a predetermined temperature so as to obtain a thick layer transferred wafer (12), which is to be regenerated.Type: ApplicationFiled: December 21, 2006Publication date: June 28, 2007Inventors: Etsurou Morita, Shinji Okawa, Isoroku Ono
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Publication number: 20070148912Abstract: There are provided a method for manufacturing a direct bonded SOI wafer in which the entire buried oxide film layer is covered and not exposed and a direct bonded SOI wafer. This is the improvement of a method for manufacturing a direct bonded SOI wafer comprising the process of (A) forming a laminated body by laminating a semiconductor wafer and a support wafer via an oxide film; and (B) forming a thin-film single crystal silicon layer on the support wafer using a buried oxide film layer by film-thinning the semiconductor wafer to a predetermined thickness, wherein in a process (C) the entire buried oxide film layer is covered by a main surface on the laminating side of the support wafer and the single crystal silicon layer.Type: ApplicationFiled: December 21, 2006Publication date: June 28, 2007Inventors: Etsurou Morita, Shinji Okawa, Isoroku Ono
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Publication number: 20070148917Abstract: The regeneration cost is reduced when a layer transferred wafer is to be reused two times or more. Ions are implanted into a semiconductor wafer (13) to form an ion implanted area (13b) inside the semiconductor wafer (13), and a first laminated body (16) in which the wafer (13) is laminated on a first support wafer (14) is subjected to heat treatment so as to obtain a thick first layer transferred wafer (12). Then, an ion implanted area (23b) is formed inside the layer transferred wafer (12) by implanting ions into a second main surface (12c) of the first layer transferred wafer (12) on the side opposite to a separated surface (12a), and a second laminated body (26) in which the main surface (12c) of the wafer (12) is laminated onto a second support wafer (24) is subjected to heat treatment so as to obtain a thick second layer transferred wafer (22). And then, both surfaces of the layer transferred wafer (22) are polished to obtain a regenerated wafer (32).Type: ApplicationFiled: December 21, 2006Publication date: June 28, 2007Inventors: Etsurou Morita, Shinji Okawa, Isoroku Ono
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Publication number: 20030181141Abstract: An object of the present invention is to provide a method of polishing semiconductor wafer by using a double-sided polisher which prevents a polish-sagging in an outer periphery of the wafer and thereby improves a degree of flatness of the semiconductor wafer. During polishing of the semiconductor wafer by using a double-sided polisher, a larger difference as compared to the prior art is created between a frictional resistance acting on a front surface of a silicon wafer W from an upper surface plate 12 side and a frictional resistance acting on a back surface of the silicon wafer W from a lower surface plate 13 side. This is because the present invention has employed a hard expanded urethane foam pad 14 and a soft non-woven fabric pad 15, which have different friction coefficients to the silicon wafer W from each other. Thereby, respective wafers W can be rotated at such a high speed as 0.1-1.0 rpm within corresponding wafer holding holes 11a.Type: ApplicationFiled: November 25, 2002Publication date: September 25, 2003Inventors: Toru Taniguchi, Isoroku Ono, Seiji Harada
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Publication number: 20030104698Abstract: An object of the present invention is to provide a semiconductor wafer having a front and a back surfaces polished so as to have different glossiness from each other, yet with a lower cost. The glossiness of the front surface and the back surface can be selected arbitrarily. In a double-sided polisher with no sun gear, silicon wafers W are inserted in respective holding holes 11a of a carrier plate 11. The wafers W are placed with their back surfaces facing up. An expanded urethane foam pad 14 is pressed against the back surfaces of the wafers W and a non-woven fabric pad 15 is pressed against the front surfaces of the wafers W. A carrier holder 20 and thus the carrier plate 11 are then driven to make a circular motion associated with no rotation on their own axes within a horizontal plane while supplying a slurry to the wafers W from an upper surface plate 12 side.Type: ApplicationFiled: October 23, 2002Publication date: June 5, 2003Inventors: Toru Taniguchi, Etsuro Morita, Satoshi Matagawa, Seiji Harada, Isoroku Ono, Mitsuhiro Endo, Fumihiko Yoshida