Patents by Inventor Israel A. Lesk

Israel A. Lesk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5927993
    Abstract: A method useful in the backside processing of semiconductor wafers includes providing a semiconductor wafer having a first surface that has been substantially processed. The processed first surface of the semiconductor wafer is bonded to a handle wafer. Once bonded to the handle wafer, backside processing may be performed on the wafer. Following backside processing, the wafer is sawn while still bonded to the handle wafer. The individual dice are then removed from the handle wafer. This process involves fewer handling steps of the semiconductor wafer and the handle wafer provides support to the semiconductor wafer during backside processing thereby reducing opportunities for breakage.
    Type: Grant
    Filed: February 3, 1992
    Date of Patent: July 27, 1999
    Assignee: Motorola, Inc.
    Inventors: Israel A. Lesk, Robert B. Davies, Robert E. Rutter, Lowell E. Clark
  • Patent number: 5908321
    Abstract: A method for making a semiconductor structure which may be subject to small particle contaminants (12) includes pre-reacting the small particle (12) with a substrate (10) at a reaction temperature (27, 28). Pre-reacting the particle's (12) greatly reduces the particles' susceptibility to further reaction during subsequent processing, particularly gate dielectric formation. Consequently, the pre-reacted particle (13) as well as the remainder of the structure surface (11) can be covered with a high quality conformal deposited dielectric (14) which maintains a uniform thickness. Potential localized high leakage current density regions are thereby reduced. Additionally, an undesirably thin gate oxide region (70) adjacent a thick field oxide region (66) of a typical MOS structure is eliminated. Yield and reliability are thereby enhanced.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: June 1, 1999
    Assignee: Motorola, Inc.
    Inventor: Israel A. Lesk
  • Patent number: 5567649
    Abstract: A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13, 14). The titanium nitride layer (17) substantially prevents dopants from diffusing into the titanium nitride (17) and subsequently counterdoping the doped areas (12, 13, 14) during subsequent high temperature processing operations.
    Type: Grant
    Filed: August 24, 1995
    Date of Patent: October 22, 1996
    Assignee: Motorola Inc.
    Inventors: Israel A. Lesk, Francine Y. Robb, Lewis E. Terry, Frank Secco d'Aragona
  • Patent number: 5556793
    Abstract: A method for gettering metallic impurities from a semiconductor substrate (25). A gettering structure is fabricated in inactive areas of a semiconductor chip (31). The gettering structure is manufactured by forming an oxide (30) having a bird's head structure contacting a heavily doped region (28). The combination creates precipitation nuclei to which the metallic impurities migrate. The metallic impurities are sequestered by the precipitation nuclei or trap sites and rendered incapable of degrading the electrical characteristics of a semiconductor device.
    Type: Grant
    Filed: November 1, 1993
    Date of Patent: September 17, 1996
    Assignee: Motorola, Inc.
    Inventors: Steven J. Adler, George W. Hawkins, Israel A. Lesk, Peter L. Pegler, Hassan Pirastehfar
  • Patent number: 5436498
    Abstract: Reactor atoms (22) are introduced into a silicon substrate (10) by ion implantation to combine with metal impurities (18) to form stable chemical compounds (24). The stable compounds do not decompose and release the metal impurities during subsequent processing steps. Such metal impurities are detrimental to semiconductor devices formed in active regions (16, 17) in the silicon substrate. The reactor atoms such as sulfur are chosen to be substantially immobile in silicon at normal semiconductor processing temperatures. The metal impurities such as iron are effectively gettered to increase performance and reliability of semiconductor devices formed in the active regions (16, 17) in the silicon substrate.
    Type: Grant
    Filed: February 4, 1994
    Date of Patent: July 25, 1995
    Assignee: Motorola, Inc.
    Inventor: Israel A. Lesk
  • Patent number: 5434442
    Abstract: A field plate avalanche diode has a field plate extending over the breakdown PN junction.
    Type: Grant
    Filed: May 11, 1992
    Date of Patent: July 18, 1995
    Assignee: Motorola, Inc.
    Inventors: Israel A. Lesk, Hassan Pirastehfar
  • Patent number: 5430327
    Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.
    Type: Grant
    Filed: September 14, 1993
    Date of Patent: July 4, 1995
    Assignee: Motorola, Inc.
    Inventors: Schyi-Yi Wu, Hang M. Liaw, Curtis D. Moyer, Steven A. Voight, Israel A. Lesk
  • Patent number: 5389576
    Abstract: A method substantially eliminating consumption of silicon from semiconductor devices is provided. The method includes controlling gases within the environment wherein the semiconductor device is positioned. The environment is formed to include an inert gas and oxygen. The oxygen content is formed to have a concentration between approximately 1.times.10.sup.1 and 1.times.10.sup.5 parts per million. Such an oxygen concentration substantially prevents converting silicon from the semiconductor device into silicon monoxide thereby substantially eliminating silicon consumption.
    Type: Grant
    Filed: December 28, 1992
    Date of Patent: February 14, 1995
    Assignee: Motorola, Inc.
    Inventor: Israel A. Lesk
  • Patent number: 5369304
    Abstract: A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13, 14). The titanium nitride layer (17) substantially prevents dopants from diffusing into the titanium nitride ( 17 ) and subsequently counterdoping the doped areas (12, 13, 14) during subsequent high temperature processing operations.
    Type: Grant
    Filed: August 14, 1992
    Date of Patent: November 29, 1994
    Assignee: Motorola, Inc.
    Inventors: Israel A. Lesk, Francine Y. Robb, Lewis E. Terry, Frank S. d'Aragona
  • Patent number: 5300187
    Abstract: Contaminants are removed from a semiconductor material by heating the semiconductor material to temperature within the range of a minimum temperature where a halogen compound will decompose to halogen atoms without the use of ultraviolet irradiation and react with contaminants present on the semiconductor material and a maximum temperature of 800.degree. C., wherein less than or equal to approximately 50 Angstroms of oxide is formed on the semiconductor material. The ambient in which the semiconductor material is heated is an ambient comprised of a nonreactive gas and a halogen compound for at least a time sufficient to remove a substantial amount of contaminants from the semiconductor material.
    Type: Grant
    Filed: September 3, 1992
    Date of Patent: April 5, 1994
    Assignee: Motorola, Inc.
    Inventors: Israel A. Lesk, Young Limb, Philip J. Tobin, John Franka, Paul T. Lin, Jonathan C. Dahm, Gary L. Huffman, Bich-Yen Nguyen
  • Patent number: 5275971
    Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.
    Type: Grant
    Filed: April 20, 1992
    Date of Patent: January 4, 1994
    Assignee: Motorola, Inc.
    Inventors: Schyi-Yi Wu, Hang M. Liaw, Curtis D. Moyer, Steven A. Voight, Israel A. Lesk
  • Patent number: 5268326
    Abstract: A dielectric and conductive isolated island is fabricated by providing an active wafer having a first and a second major surface, a doped region extending from the first surface, and a trench formed at the first surface. A conductive layer is formed on the first surface and in the trench. A planarizable layer comprised of a dielectric layer is then formed on the conductive layer. A handle wafer is bonded to the planarizable layer. The active wafer and the handle wafer are heated so that the doped region diffuses along the conductive layer to form an equalized concentration of dopant along the conductive layer which diffuses into the active wafer to form the doped region adjacent all of the conductive layer. A portion of the second surface of the active wafer is then removed so that at least a portion of the dielectric layer of the planarizable layer is exposed.
    Type: Grant
    Filed: September 28, 1992
    Date of Patent: December 7, 1993
    Assignee: Motorola, Inc.
    Inventors: Israel A. Lesk, Frank S. d'Aragona, Francine Y. Robb, Raymond C. Wells
  • Patent number: 5119171
    Abstract: An improved semiconductor die for plastic encapsulated semiconductor device packages which impedes the inherent delamination caused by the differing expansion coefficients of the semiconductor die and plastic encapsulation. Rounded or tapered die corners and die edges decrease the stress from the plastic encapsulation that acts upon the semiconductor die. This reduced stress slows the delamination progression and leaves the operational circuitry unaffected for an increased period of time thereby increasing device lifetime.
    Type: Grant
    Filed: March 22, 1991
    Date of Patent: June 2, 1992
    Assignee: Motorola, Inc.
    Inventors: Israel A. Lesk, Ronald E. Thomas, George W. Hawkins
  • Patent number: 4928162
    Abstract: An improved semiconductor die for plastic encapsulated semiconductor devices which impedes the inherent delamination caused by the differing expansion coefficients of the semiconductor die and plastic encapsulation. Topological configurations are processed in the die corners of the semiconductor die which are void of circuitry. The topological configurations act as barriers and slow the delamination progression. This leaves the operational circuitry unaffected for an increased time thereby increasing device lifetime.
    Type: Grant
    Filed: February 22, 1988
    Date of Patent: May 22, 1990
    Assignee: Motorola, Inc.
    Inventors: Israel A. Lesk, Ronald E. Thomas, George W. Hawkins, James M. Rugg
  • Patent number: 4924291
    Abstract: A molded semiconductor package having a flagless leadframe wherein a semiconductor die is disposed in or above a die opening of a leadframe. This allows for thin, symmetrical packages and packages having a minimum number of material interfaces to be manufactured because no leadframe flags and minimal die bond material are employed. The present invention further includes guard rings to protect high stress areas of the semiconductor die from damage and heat spreaders to more effectively spread heat dissipated by the semiconductor die.
    Type: Grant
    Filed: October 24, 1988
    Date of Patent: May 8, 1990
    Assignee: Motorola Inc.
    Inventors: Israel A. Lesk, George W. Hawkins, Ronald E. Thomas, William L. Hunter, James J. Casto, Michael B. McShane
  • Patent number: 4916082
    Abstract: Charge on a floating gate of a semiconductor device structure is neutralized by illuminating the structure with a high intensity light during process steps that inject charge. The light provides for the formation of electrons, or free carriers, in the semiconductor substrate. The electrons facilitate tunneling which prevents dielectric degradation or rupture.
    Type: Grant
    Filed: March 14, 1989
    Date of Patent: April 10, 1990
    Assignee: Motorola Inc.
    Inventors: Israel A. Lesk, Clarence A. Lund, Thomas C. Smith
  • Patent number: 4905070
    Abstract: The degradation of the low current gain, which is exhibited during emitter-base reverse bias breakdown testing, is prevented by providing an emitter-base resistive shunt on the surface. This resistive shunt, preferably made of silicon nitride. utilizes surface recombination to reduce the low current gain permanently, thus a degradation is not exhibited upon testing.
    Type: Grant
    Filed: September 2, 1988
    Date of Patent: February 27, 1990
    Assignee: Motorola, Inc.
    Inventors: Israel A. Lesk, Peter J. Zdebel, Han-Bin K. Liang
  • Patent number: 4881115
    Abstract: A semiconductor device having a conductive recombination layer. The conductive recombination layer, comprised of doped polycrystalline material, doped polycrystalline material and tungsten silicide, or tungsten silicide, is disposed between two separate semiconductor substrates which are bonded together using a polished surface on the conductive recombination layer as one of the bonding interfaces. The conductive recombination layer recombines minority carriers and thereby increases the switching speed of the device.
    Type: Grant
    Filed: February 21, 1989
    Date of Patent: November 14, 1989
    Assignee: Motorola Inc.
    Inventors: Israel A. Lesk, Lowell E. Clark
  • Patent number: 4837177
    Abstract: A semiconductor device having a conductive recombination layer. The conductive recombination layer, comprised of doped polycrystalline material, doped polycrystalline material and tungsten silicide, or tungsten silicide, is disposed between two separate semiconductor substrates which are bonded together using a polished surface on the conductive recombination layer as one of the bonding interfaces. The conductive recombination layer recombines minority carriers and thereby increases the switching speed of the device.
    Type: Grant
    Filed: December 28, 1987
    Date of Patent: June 6, 1989
    Assignee: Motorola Inc.
    Inventors: Israel A. Lesk, Lowell E. Clark
  • Patent number: 4832996
    Abstract: A semiconductor die for plastic encapsulation having an adhesion promoter selectively disposed on an outer surface enabling better adhesion between the semiconductor die and a plastic encapsulation. The improved adhesion allows for less relative motion between the semiconductor die and the plastic encapsulation. The reduction of relative motion significantly decreases the delamination progression throughout the semiconductor device and allows for an increased semiconductor device lifetime.
    Type: Grant
    Filed: February 24, 1988
    Date of Patent: May 23, 1989
    Assignee: Motorola, Inc.
    Inventors: Israel A. Lesk, Ronald E. Thomas, George W. Hawkins