Abstract: In one embodiment, a processor includes: one or more cores to execute instructions; a first request register to store hardware performance state control information for a first core of the one or more cores obtained from an operating system; a second request register to store hardware performance state control override information, the hardware performance state control override information to be received from a management controller coupled to the processor; and a power controller coupled to the one or more cores to control a performance state of the first core based at least in part on the hardware performance state override information when at least one override indicator of the second request register is set. Other embodiments are described and claimed.

Abstract: Technologies are provided in embodiments to dynamically bias performance of logical processors in a core of a processor. One embodiment includes identifying a first logical processor associated with a first thread of an application and a second logical processor associated with a second thread, obtaining first and second thread preference indicators associated with the first and second threads, respectively, computing a first relative performance bias value for the first logical processor based, at least in part, on a relativeness of the first and second thread preference indicators, and adjusting a performance bias of the first logical processor based on the first relative performance bias value. Embodiments can further include increasing the performance bias of the first logical processor based, at least in part, on the first relative performance bias value indicating a first performance preference that is higher than a second performance preference.

Abstract: In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes: one or more cores to execute instructions; a first request register to store hardware performance state control information for a first core of the one or more cores obtained from an operating system; a second request register to store hardware performance state control override information, the hardware performance state control override information to be received from a management controller coupled to the processor; and a power controller coupled to the one or more cores to control a performance state of the first core based at least in part on the hardware performance state override information when at least one override indicator of the second request register is set. Other embodiments are described and claimed.

Abstract: Technologies are provided in embodiments to dynamically bias performance of logical processors in a core of a processor. One embodiment includes identifying a first logical processor associated with a first thread of an application and a second logical processor associated with a second thread, obtaining first and second thread preference indicators associated with the first and second threads, respectively, computing a first relative performance bias value for the first logical processor based, at least in part, on a relativeness of the first and second thread preference indicators, and adjusting a performance bias of the first logical processor based on the first relative performance bias value. Embodiments can further include increasing the performance bias of the first logical processor based, at least in part, on the first relative performance bias value indicating a first performance preference that is higher than a second performance preference.

Abstract: In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.

Abstract: Machine-readable media, methods, apparatus and system for booting a processing system are described. In an embodiment, whether to launch an open operating system or a closed operating system to boot a processing system may be determined. A key may be retrieved from a processor register of the processing system and used to decrypt an encrypted version of the closed operating system based at least in part on a determination of booting the processing system with the closed operating system. In another embodiment, the processor register stored with the key may be flushed based at least in part on a determination of booting the processing system with the open operating system.

Abstract: Machine-readable media, methods, apparatus and system for booting a processing system are described. In an embodiment, whether to launch an open operating system or a closed operating system to boot a processing system may be determined. A key may be retrieved from a processor register of the processing system and used to decrypt an encrypted version of the closed operating system based at least in part on a determination of booting the processing system with the closed operating system. In another embodiment, the processor register stored with the key may be flushed based at least in part on a determination of booting the processing system with the open operating system.

Abstract: Machine-readable media, methods, apparatus and system for booting a processing system are described. In an embodiment, whether to launch an open operating system or a closed operating system to boot a processing system may be determined. A key may be retrieved from a processor register of the processing system and used to decrypt an encrypted version of the closed operating system based at least in part on a determination of booting the processing system with the closed operating system. In another embodiment, the processor register stored with the key may be flushed based at least in part on a determination of booting the processing system with the open operating system.

Abstract: In one embodiment, an optimized interleaving instruction is provided. The interleaving instruction facilitates a bit-level interleaving of two streams of data stored in two source registers into a combined stream of data.

Abstract: In one embodiment, an optimized interleaving instruction is provided. The interleaving instruction facilitates a bit-level interleaving of two streams of data stored in two source registers into a combined stream of data.

Abstract: In one embodiment, an optimized interleaving instruction is provided. The interleaving instruction facilitates a bit-level interleaving of two streams of data stored in two source registers into a combined stream of data.

Abstract: In one embodiment, an optimized interleaving instruction is provided. The interleaving instruction facilitates a bit-level interleaving of two streams of data stored in two source registers into a combined stream of data.