Abstract: An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) cell array and a first assist circuit and a differently configured second assist circuit. The first assist circuit is configured to apply a voltage boost to an access line utilized to access the SRAM cell array, and the second assist circuit is configured to apply a voltage boost to a voltage supply rail of the SRAM cell array. A common boost capacitor is coupled to selectively and concurrently provide a voltage boost to both the access line and the power rail via the first and second assist circuits, respectively.

Abstract: A clock gating method and circuit for avoiding out-of-spec clock operations. The circuit comprises a clock gating section that gates a clock signal according to an enabling signal generated by an enabling signal controller, the enabling signal controller generating the enabling signal according to a set signal and a reset signal. The circuit further comprises a set signal generator that generates the set signal, a reset signal generator that generates the reset signal, and a feedback section that uses the enabling signal to generate the feedback signal for the reset signal generator. The reset signal generator generates the reset signal by using the feedback signal. The enabling signal controller further generates an acknowledgement signal having a high signal during a blocking period when the clock signal is blocked and utilizes the acknowledgement signal as an announcement to a higher circuit that the clock signal is blocked.

Abstract: An electrical circuit includes a driver circuit, a receiver circuit, and a keeper circuit. The receiver circuit receives an input pulse from the driver circuit during a pre-charge phase. The receiver circuit generates an output pulse based on the input pulse during an evaluation phase. The keeper circuit maintains a charge of the output pulse until another evaluation phase, wherein the keeper circuit is adapted to the driver circuit by gating a first voltage supply of the driver circuit with a second voltage supply of the keeper circuit.

Abstract: An electrical circuit includes a driver circuit, a receiver circuit, and a keeper circuit. The receiver circuit receives an input pulse from the driver circuit during a pre-charge phase. The receiver circuit generates an output pulse based on the input pulse during an evaluation phase. The keeper circuit maintains a charge of the output pulse until another evaluation phase, wherein the keeper circuit is adapted to the driver circuit by gating a first voltage supply of the driver circuit with a second voltage supply of the keeper circuit.

Abstract: In an approach utilizing static analysis, a processor receives a netlist for an integrated circuit. For at least one node of the integrated circuit in the netlist, a processor calculates (i) a total capacitive load of the respective node and (ii) a minimum required driver size. For a driver of the respective node, a processor (i) determines an effective driver size of the driver based on at least a number of fins of the driver and (ii) determines that the effective driver size exceeds the minimum required driver size multiplied by a predefined sizing margin. A processor, responsive to determining that the effective driver size exceeds the minimum required driver size multiplied by the predefined sizing margin, generates a report, where the report includes at least the driver and a suggestion to reduce the effective size of the driver.

Abstract: In an approach utilizing static analysis, a processor receives a netlist for an integrated circuit. For at least one node of the integrated circuit in the netlist, a processor calculates (i) a total capacitive load of the respective node and (ii) a minimum required driver size. For a driver of the respective node, a processor (i) determines an effective driver size of the driver based on at least a number of fins of the driver and (ii) determines that the effective driver size exceeds the minimum required driver size multiplied by a predefined sizing margin. A processor, responsive to determining that the effective driver size exceeds the minimum required driver size multiplied by the predefined sizing margin, generates a report, where the report includes at least the driver and a suggestion to reduce the effective size of the driver.

Abstract: A method, system and product including adapting a value of a delay parameter that is utilized in an operation of a memory-cell array, wherein the delay parameter influences a ratio between an operation portion of a clock cycle and a pre-charge portion of the clock cycle, wherein writing or reading to the memory-cell array is enabled during the operation portion of the clock cycle and is disabled during the pre-charge portion of the clock cycle, wherein said adapting comprises: initializing the delay parameter with an initial value; writing a first test data into the memory-cell array; attempting to read from the memory-cell array a second test data; comparing the first test data with the second test data; and selecting a target value for the delay parameter based on said comparing.

Abstract: An approach for detecting potential failures and sensitivities, based on preliminary verification of timing circuits which includes feedback and combinatorial loops for is disclosed. The approach comprises relating timing events by algebraic equations, breaking loops, and feedbacks by backward reference, and then propagate signals through time and netlist.

Abstract: An example computer-implemented method includes receiving hardware testing results, an address, input/output (I/O) data, a redundancy status, and an input-memory-output mapping corresponding to a memory being tested. The method includes locating a failed cell of the memory based on the hardware testing results, the address, the input/output data, the redundancy status, and the input-memory-output mapping. The method also includes automatically repairing the failed cell.

Abstract: A dynamic capacitor circuit having a first passive capacitor, a second passive capacitor, a first terminal of the first passive capacitor and a first terminal of the second passive capacitor connected together to receive an input signal through a resistor. The input signal includes a noise signal component. An alternating current (AC) coupled inverting amplifier has an input connecting a second terminal of the second passive capacitor, the second capacitor coupling the input signal to the AC coupled inverting amplifier input. A conductive path couples an output of the AC coupled inverting amplifier to a second terminal of the first passive capacitor to balance out any noise signal component of the input AC signal at the connection. The dynamic capacitor achieves an amount of noise reduction in a reduced space without applying deep trench capacitors (DTCAP) where the DTCAP is a capacitance formed in a plane perpendicular to the substrate.

Abstract: An example computer-implemented method includes receiving hardware testing results, an address, input/output (I/O) data, a redundancy status, and an input-memory-output mapping corresponding to a memory being tested. The method includes locating a failed cell of the memory based on the hardware testing results, the address, the input/output data, the redundancy status, and the input-memory-output mapping. The method also includes automatically repairing the failed cell.

Abstract: A voltage-controlled delay line including a clipper configured to produce a clipped input voltage from an input voltage, an oscillator configured to produce a strobe pulse train that is initiated by the clipped input voltage, and a divider module configured to divide the strobe pulse train and produce an output voltage from the divided strobe pulse train.

Abstract: A design structure can include elements that, when processed in a semiconductor manufacturing facility, produce an SRAM that includes a first local evaluator coupled to a first global bit line (GBL) and a first set of local bit lines (LBLs). The SRAM can also include a second local evaluator communicatively coupled to the first local evaluator. The second local evaluator is coupled to a second GBL and second set of LBLs. The second GBL is consecutive to the first GBL. The first and second evaluators are to generate signals from the LBLs such that one GBL of a combined first and second GBLs is active at any point in a read or write cycle.

Abstract: A method in a computer-aided design system for generating a functional design model of a static random access memory is described herein. The method comprises generating a functional representation of a first local evaluation logic coupled to a first set of consecutive global bit lines (GBLs) and a first set of local bit lines (LBLs), the first local evaluation logic comprising a plurality of devices. The method further comprises generating a functional representation of a second local evaluation logic communicatively coupled to the first local evaluation logic via the devices; the second local evaluation logic is coupled to a second set of consecutive GBLs and a second set of LBLs. In addition, the second set of consecutive GBLs consecutive to the first set of consecutive GBLs, the first and second evaluation logics to generate signals from the LBLs such that one GBL is to be active at any point in a read or write cycle and the other GBLs are not concurrently active.

Abstract: A novel and useful direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability. The DMRO circuit uses an un-modified SRAM cell in each delay stage of the oscillator. A small amount of external circuitry is added to allow the ring to oscillate and detect read instability errors. An external frequency counter is the only equipment that is required, as there is no need to obtain an exact delay measurement and use a precise waveform generator. The DMRO circuit monitors the delay and stability of an SRAM cell within its real on-chip operating neighborhood. The advantage provided by the circuit is derived from the fact that measuring the frequency of a ring oscillator is easier than measuring the phase difference of signals or generating signals with precise phase, and delivering such signals to/from the chip. In addition, the DMRO enables monitoring of read stability failures.

Abstract: A method for testing a circuit comprising a memory element, a voltage comparator and a supply selector, the circuit is configured to be connected to two power supplies, the voltage comparator is configured to provide an output indicative of a voltage difference between the two power supplies above a predetermined threshold, the supply selector is configured to select a power supply to feed power to the memory element in response to the output from the voltage comparator. The method comprises connecting the two power supplies to the circuit, wherein said connecting comprises causing the two power supplies to drive power to the memory element and to another element of the circuit, wherein the voltage different between the two power supplies is above the predetermined threshold.

Abstract: A circuit comprising a first power supply having a first voltage and a second power supplying having a second voltage, wherein said first and second voltages are different at least in some cycles of said circuit, a memory element, wherein said first and second power supplies are driven into said memory element, a voltage comparator having connected thereto said first and second power supplies, wherein said voltage comparator is an analog to digital converter configured to provide digital output indicting of a voltage difference over a predetermined threshold between said first and second power supplies, and a supply selector element, wherein said supply selector element is configured to disconnect said second power supply from said memory element in response to the digital output of said voltage comparator.

Abstract: A method for testing a circuit comprising a memory element, a voltage comparator and a supply selector, the circuit is configured to be connected to two power supplies, the voltage comparator is configured to provide an output indicative of a voltage difference between the two power supplies above a predetermined threshold, the supply selector is configured to select a power supply to feed power to the memory element in response to the output from the voltage comparator. The method comprises connecting the two power supplies to the circuit, wherein said connecting comprises causing the two power supplies to drive power to the memory element and to another element of the circuit, wherein the voltage different between the two power supplies is above the predetermined threshold.

Abstract: A novel and useful direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability. The DMRO circuit uses an unmodified SRAM cell in each delay stage of the oscillator. A small amount of external circuitry is added to allow the ring to oscillate and detect read instability errors. An external frequency counter is the only equipment that is required, as there is no need to obtain an exact delay measurement and use a precise waveform generator. The DMRO circuit monitors the delay and stability of an SRAM cell within its real on-chip operating neighborhood. The advantage provided by the circuit is derived from the fact that measuring the frequency of a ring oscillator is easier than measuring the phase difference of signals or generating signals with precise phase, and delivering such signals to/from the chip. In addition, the DMRO enables monitoring of read stability failures.

Abstract: A circuit comprising a first power supply having a first voltage and a second power supplying having a second voltage, wherein said first and second voltages are different at least in some cycles of said circuit, a memory element, wherein said first and second power supplies are driven into said memory element, a voltage comparator having connected thereto said first and second power supplies, wherein said voltage comparator is an analog to digital converter configured to provide digital output indicting of a voltage difference over a predetermined threshold between said first and second power supplies, and a supply selector element, wherein said supply selector element is configured to disconnect said second power supply from said memory element in response to the digital output of said voltage comparator.