Abstract: A circuit is disclosed for receiving or transmitting signals from or to different receiving or transmitting members. More particularly, the circuit includes, a microprocessor for at least unscrambling and demultiplexing, and a switching matrix for transmitting or receiving different data flows to or from various receiving or transmitting members. The switching matrix having at least a parallel type connection formed by a plurality of conductors and a serial type connection. Certain conductors of a parallel type connection serve at the same time for the serial type connections, and the circuit is provided with logic elements for controlling the switching of the signals corresponding to serial type connections to conductors provided for the signals corresponding to the parallel type connections, as desired.

Abstract: In a video-communication receiver provided with a deciphering module (13) used for the descrambling of scrambled transmissions, using a memory card (17) for providing information required for descrambling, service information is introduced into the receiver, for example, by replacing the memory card by a service card containing the information in a ciphered form. The receiver is provided with apparatus (29, 12, 31) for deciphering ciphered service information by means of its own deciphering module (13).

Abstract: For dynamically modifying pseudo-random sequences of a pseudo-random sequence generator which is re-initialized at each start of the packet of information components, the information component itself is derived, delayed and combined with one of the series of bits present in the pseudo-random sequence generator. After having delayed the derived information component by a given delay (20), the component is modified by passing it through an EXCLUSIVE-OR gate (23) and by delaying the output signal of said gate with a delay (21) equal to that (20) used for said derived information component, and by feeding it back to the input of the gate.

Abstract: A system which provides synchronization with frame synchronization words of a partially digital signal, such as that of the D2MAC television standard. It is provided that three modes of operation are established sequentially. In a first mode, the values necessary to control the gain and the d.c. level of the television signal are obtained by means of a peak detector (18). Similarly, in a second mode, the peak detector is enabled only during the digital signal periods of the D2MAC signal. Finally, in the third mode, the setting values are obtained by arrangements (13, 8) which depend on the clamp plateau measurement of each line and of line 624.