Abstract: To provide a technique for detecting a low voltage of a power-on reset circuit. A semiconductor device has a power-on reset circuit including: a first bipolar transistor; a second bipolar transistor formed by connecting a plurality of bipolar transistors in parallel; a detection-voltage adjusting resistance element; a temperature-characteristic adjusting resistance element; a current adjusting resistance element; and a comparator.

Abstract: To provide a technique for detecting a low voltage of a power-on reset circuit. A semiconductor device has a power-on reset circuit including: a first bipolar transistor; a second bipolar transistor formed by connecting a plurality of bipolar transistors in parallel; a detection-voltage adjusting resistance element; a temperature-characteristic adjusting resistance element; a current adjusting resistance element; and a comparator.

Abstract: A plurality of IO cells are arranged along an edge portion of a semiconductor chip. Some elements forming a reference voltage generation circuit are arranged in a first corner region of the semiconductor chip. Remaining elements forming the reference voltage generation circuit are arranged in a core region on an inner side of the edge portion of the semiconductor chip. Among a plurality of corner regions, the first corner region is located closest to the remaining elements.

Abstract: A voltage monitoring circuit and a semiconductor device that can reduce time required for self-diagnosis are provided. A selection circuit selects one of a determination threshold voltage for normal use, a determination threshold voltage for self-diagnosis, and a determination threshold voltage for boost having a potential difference larger than that of the determination threshold voltage for normal use. A comparison circuit detects a presence or absence of a specification violation of the voltage to be monitored by comparing a selected voltage selected by the selection circuit and the voltage to be monitored.

Abstract: A plurality of IO cells are arranged along an edge portion of a semiconductor chip. Some elements forming a reference voltage generation circuit are arranged in a first corner region of the semiconductor chip. Remaining elements forming the reference voltage generation circuit are arranged in a core region on an inner side of the edge portion of the semiconductor chip. Among a plurality of corner regions, the first corner region is located closest to the remaining elements.

Abstract: A plurality of IO cells are arranged along an edge portion of a semiconductor chip. Some elements forming a reference voltage generation circuit are arranged in a first corner region of the semiconductor chip. Remaining elements forming the reference voltage generation circuit are arranged in a core region on an inner side of the edge portion of the semiconductor chip. Among a plurality of corner regions, the first corner region is located closest to the remaining elements.

Abstract: A plurality of IO cells are arranged along an edge portion of a semiconductor chip. Some elements forming a reference voltage generation circuit are arranged in a first corner region of the semiconductor chip. Remaining elements forming the reference voltage generation circuit are arranged in a core region on an inner side of the edge portion of the semiconductor chip. Among a plurality of corner regions, the first corner region is located closest to the remaining elements.

Abstract: To prevent the influence of variations in reference voltage until a power source is activated in a semiconductor device including a reference voltage generating circuit that can be adjusted by trimming data. In a semiconductor device, a reference voltage generating unit generates a first reference voltage adjusted in accordance with trimming data and a second reference voltage that does not depend on the trimming data based on an external power source voltage. A nonvolatile memory operates in accordance with a voltage based on the first reference voltage and stores the trimming data. A power-on reset circuit switches logic levels of a reset signal when the external power source voltage reaches a constant multiple of the second reference voltage at the time of activation of power source. A control circuit causes the reference voltage generating unit to read the trimming data stored in the nonvolatile memory in response to the switching of the logic levels of the reset signal.

Abstract: The present invention provides a semiconductor chip which is insusceptible to noise and whose consumption current is small. In a semiconductor chip, an internal power supply voltage for an internal circuit block is generated by a regulator having small current drive capability and a regulator having large current drive capability. A voltage buffer is provided between a reference voltage generating circuit and the regulator having large current drive capability. In a low-speed operation mode, the voltage buffer and the regulator having large current drive capability are made inactive. Therefore, noise in reference voltage is suppressed, and consumption current can be reduced.

Abstract: To prevent the influence of variations in reference voltage until a power source is activated in a semiconductor device including a reference voltage generating circuit that can be adjusted by trimming data. In a semiconductor device, a reference voltage generating unit generates a first reference voltage adjusted in accordance with trimming data and a second reference voltage that does not depend on the trimming data based on an external power source voltage. A nonvolatile memory operates in accordance with a voltage based on the first reference voltage and stores the trimming data. A power-on reset circuit switches logic levels of a reset signal when the external power source voltage reaches a constant multiple of the second reference voltage at the time of activation of power source. A control circuit causes the reference voltage generating unit to read the trimming data stored in the nonvolatile memory in response to the switching of the logic levels of the reset signal.

Abstract: The present invention provides a semiconductor chip which is insusceptible to noise and whose consumption current is small. In a semiconductor chip, an internal power supply voltage for an internal circuit block is generated by a regulator having small current drive capability and a regulator having large current drive capability. A voltage buffer is provided between a reference voltage generating circuit and the regulator having large current drive capability. In a low-speed operation mode, the voltage buffer and the regulator having large current drive capability are made inactive. Therefore, noise in reference voltage is suppressed, and consumption current can be reduced.