Patents by Inventor ISTVAN BAUER

ISTVAN BAUER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210181253
    Abstract: A method for failed die clustering is provided that includes extracting a data set of failed die on a wafer from a wafer map for the wafer, determining a density parameter for clustering the failed die, removing false failures from the data set of failed die to generate a reduced data set of failed die, locating clusters of failed die in the reduced data set by executing a density-based spatial clustering of applications with noise (DBSCAN) algorithm with the density parameter, and applying a guard band to each located cluster.
    Type: Application
    Filed: November 12, 2020
    Publication date: June 17, 2021
    Inventors: Istvan Bauer, Michael Menne Haggerty, Scott Eric Riddle, Peter W. Kinghorn, Amit Nahar, Glenn Edward Schuette, Russell K. Kneupper
  • Patent number: 9606178
    Abstract: A method of probing wafers includes providing a processor running a parametric test program generator algorithm which execute steps including reading a stored first probe program including a first test sequence (TS1) having a first tests configured for probing at least a first circuit element (FCE) in a first scribe line module. TS1 includes (i) electrical pinning and geometrical data and (ii) first Variable Group data specific for the FCE including first test parameters having at least first forcing conditions. The (ii) is modified with modified second variable group data specific to a second circuit element (SCE) in a second scribe line module. The modified second Variable Group data includes modified second test parameters having second forcing conditions. (i) of TS1 is merged with the modified second Variable Group data to generate code for a second test sequence of a second probe program that is configured for probing the SCE.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: March 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Uwe Peter Schiessl, Shannon Anthony Wilmes, Istvan Bauer
  • Publication number: 20150253380
    Abstract: A method of probing wafers includes providing a processor running a parametric test program generator algorithm which execute steps including reading a stored first probe program including a first test sequence (TS1) having a first tests configured for probing at least a first circuit element (FCE) in a first scribe line module. TS1 includes (i) electrical pinning and geometrical data and (ii) first Variable Group data specific for the FCE including first test parameters having at least first forcing conditions. The (ii) is modified with modified second variable group data specific to a second circuit element (SCE) in a second scribe line module. The modified second Variable Group data includes modified second test parameters having second forcing conditions. (i) of TS1 is merged with the modified second Variable Group data to generate code for a second test sequence of a second probe program that is configured for probing the SCE.
    Type: Application
    Filed: July 29, 2014
    Publication date: September 10, 2015
    Inventors: UWE PETER SCHIESSL, SHANNON ANTHONY WILMES, ISTVAN BAUER