Patents by Inventor Istvan Vadasz

Istvan Vadasz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9674117
    Abstract: The present invention relates to a computing apparatus as an element of a network structure using a method for acquiring and maintaining cell locked data transfer amongst a number of computing apparatuses. A predefined number of symbols transmitted as a cell is followed by a variable number of idle symbols to ensure the nominally simultaneous start of the cell transfers throughout the network without a central control. At specific positions of the cells each computing apparatus broadcasts a list of its transmission requests and receiver capabilities to all other computing apparatuses. Each of the interconnected computing apparatuses executes the same arbitration procedure based on the identical data set of transmission requests and receiver capabilities. As a result transmission paths are assigned for direct transmission and for payload forwarding. The transmission paths can be assigned per cell period individually for both directions of each link.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: June 6, 2017
    Inventor: Istvan Vadasz
  • Publication number: 20160191419
    Abstract: The present invention relates to computing apparatus as an element of a network structure using a method for acquiring and maintaining cell locked data transfer amongst a number of computing apparatuses which can be full mesh interconnected by full duplex data transfer links. A predefined number of symbols transmitted as a cell is followed by a variable number of idle symbols to ensure the nominally simultaneous start of the cell transfers throughout the network without a central control. At specific positions of the cells each computing apparatus broadcasts a list of its transmission requests and receiver capabilities to all other computing apparatuses. Each of the interconnected computing apparatuses executes the same arbitration procedure based on the identical data set of transmission requests and receiver capabilities. As a result transmission paths are assigned for direct transmission and for payload forwarding.
    Type: Application
    Filed: September 9, 2015
    Publication date: June 30, 2016
    Inventor: Istvan Vadasz
  • Patent number: 9154332
    Abstract: A computing apparatus as an element of a network structure acquires and maintains cell locked data transfer amongst a number of computing apparatuses which can be full mesh interconnected by full duplex data transfer links. A predefined number of symbols transmitted as a cell is followed by a variable number of idle symbols to ensure the nominally simultaneous start of the cell transfers throughout the network. At specific positions of the cells each computing apparatus broadcasts a list of its transmission requests and receiver capabilities to all other computing apparatuses. Each of the interconnected computing apparatuses executes the same arbitration procedure based on the identical data set of transmission requests and receiver capabilities. As a result transmission paths are assigned for direct transmission and for payload forwarding. Transmission paths can be assigned per cell period individually for both directions of each link.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: October 6, 2015
    Inventor: István Vadász
  • Publication number: 20130039207
    Abstract: The present invention relates to computing apparatus as an element of a network structure using a method for acquiring and maintaining cell locked data transfer amongst a number of computing apparatuses which can be full mesh interconnected by full duplex data transfer links. A predefined number of symbols transmitted as a cell is followed by a variable number of idle symbols to ensure the nominally simultaneous start of the cell transfers throughout the network without a central control. At specific positions of the cells each computing apparatus broadcasts a list of its transmission requests and receiver capabilities to all other computing apparatuses. Each of the interconnected computing apparatuses executes the same arbitration procedure based on the identical data set of transmission requests and receiver capabilities. As a result transmission paths are assigned for direct transmission and for payload forwarding.
    Type: Application
    Filed: April 8, 2011
    Publication date: February 14, 2013
    Inventor: István Vadász
  • Patent number: 6814582
    Abstract: There is provided a system for connecting signals between at least two electronic modules. The interconnection conduits are provided via one or more blades, which are equipped with connection areas along their edge toward the modules. This structure opens up more room for high frequency signaling connections. The blades used for the interconnect can be replaced in a live system during operational conditions.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: November 9, 2004
    Assignee: Force Computers, Inc.
    Inventors: Istvan Vadasz, Stefan Hofmann
  • Publication number: 20040092168
    Abstract: There is provided a system for connecting signals between at least two electronic modules. The interconnection conduits are provided via one or more blades, which are equipped with connection areas along their edge toward the modules. This structure opens up more room for high frequency signaling connections. The blades used for the interconnect can be replaced in a live system during operational conditions.
    Type: Application
    Filed: November 8, 2002
    Publication date: May 13, 2004
    Applicant: FORCE COMPUTERS, INC.
    Inventors: Istvan Vadasz, Stefan Hofmann
  • Patent number: 6604164
    Abstract: Disclosed is a computer having a plurality of adapter cards which are insertable in adjacent bus segments, which are routed interleaved in the middle of a backplane and standard connectors are provided with connections alternating between the two bus segments. Both bus segments are connected to each other by a bridge circuit which includes at least one CPU adapter card. The invention is characterized by two bridge members each of which has an I/O unit and a CPU unit which are fixedly connected to each other. They are insertable in the bus segments with the I/O units inserted in one bus segment and the CPU units inserted in the other bus segment.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: August 5, 2003
    Assignee: Force Computers GmbH
    Inventor: Istvan Vadasz