Patents by Inventor Itai Derman

Itai Derman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reduction of output undershoot in low-current voltage regulators
    Patent number: 10025334
    Abstract: An electronic circuit includes a voltage regulator and an undershoot reduction circuit. The undershoot reduction circuit is configured to receive an indication of an event that potentially causes an undershoot in an output of the voltage regulator, and, in response to the indication, to generate and couple to the output of the voltage regulator a pulse that reduces the undershoot.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: July 17, 2018
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Itai Derman
  • REDUCTION OF OUTPUT UNDERSHOOT IN LOW-CURRENT VOLTAGE REGULATORS
    Publication number: 20180188753
    Abstract: An electronic circuit includes a voltage regulator and an undershoot reduction circuit. The undershoot reduction circuit is configured to receive an indication of an event that potentially causes an undershoot in an output of the voltage regulator, and, in response to the indication, to generate and couple to the output of the voltage regulator a pulse that reduces the undershoot.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Inventor: Itai Derman
  • Memory device with sense amplifier that sets the voltage drop across the cells of the device
    Patent number: 6141246
    Abstract: The logic state stored in a memory cell having a Frohmann-Bentchkowsky p-channel memory transistor and a n-channel MOS access transistor is read by a sense amplifier which senses the magnitude of the current output from the memory cell during a read operation. The sense amplifier controls the voltage drop across the memory transistor and the access transistor (and a switching transistor) which, in turn, allows the difference in the magnitudes of the current from the programmed and unprogrammed cells to be optimized.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: October 31, 2000
    Assignee: National Semiconductor Corporation
    Inventors: Itai Derman, Moshe Meyassed, Alexander Kalnitsky
  • Memory cell with a Frohmann-Bentchkowsky EPROM memory transistor that reduces the voltage across an unprogrammed memory transistor during a read
    Patent number: 6118691
    Abstract: The unintentional programming of a memory cell having a Frohmann-Bentchkowsky p-channel memory transistor and an n-channel MOS access transistor, which can occur during a read operation when high read voltages are used, is eliminated by forming a diode-connected MOS transistor in parallel with the access transistor. The diode-connected transistor is formed to be off when an unprogrammed memory transistor is read, and to be on when a programmed memory transistor is read.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: September 12, 2000
    Assignee: National Semiconductor Corporation
    Inventors: Alexander Kalnitsky, Itai Derman, Moshe Meyassed