Patents by Inventor Itai Dror
Itai Dror has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9817605Abstract: A method performed in a host device includes receiving an input based on a user-visible code associated with a data storage device. The user-visible code corresponds to an identifier of the data storage device. The method includes sending first data associated with the identifier to a server via a network and receiving, from the server at a first time, a copy of second data identifying content stored in the data storage device. The second data is stored in a network-based storage device associated with the server. The method includes displaying, via a user interface of the host device, an indication of the content of the data storage device to enable the content of the data storage device to be identified at the host device independently of whether the data storage device is coupled to the host device.Type: GrantFiled: January 15, 2014Date of Patent: November 14, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Michael Fellner, Itai Dror
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Patent number: 9787327Abstract: A device includes a controller, and the controller includes a root detection circuit having multiple sets of multipliers. A method includes configuring the root detection circuit according to a degree of a polynomial. In response to detection of a root of multiple roots of the polynomial, a configuration of the root detection circuit is modified based on a polynomial degree reduction (PDR) scheme. Depending on the particular implementation, the device may be implemented in a data storage device, a communication system (e.g., a wireless communication device or a wired communication device), or another electronic device.Type: GrantFiled: May 7, 2015Date of Patent: October 10, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Xinmiao Zhang, Itai Dror
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Patent number: 9507706Abstract: A memory system comprising a non-volatile memory and a controller in communication with the non-volatile memory is disclosed. The controller may include a central processing unit (“CPU”) and an internal cache in communication with the CPU via a plurality of cache lines. The CPU is configured to utilize a first subset of the plurality of cache lines when accessing data stored in the internal cache at a first resolution. Additionally, the CPU is configured to utilize a second subset of the plurality of cache lines when accessing data stored in the internal case at a second resolution, where the first and second resolutions are different resolutions.Type: GrantFiled: December 3, 2013Date of Patent: November 29, 2016Assignee: SanDisk Technologies LLCInventors: Mark Fiterman, Yoav Weinberg, Itai Dror
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Publication number: 20160329911Abstract: A device includes a controller, and the controller includes a root detection circuit having multiple sets of multipliers. A method includes configuring the root detection circuit according to a degree of a polynomial. In response to detection of a root of multiple roots of the polynomial, a configuration of the root detection circuit is modified based on a polynomial degree reduction (PDR) scheme. Depending on the particular implementation, the device may be implemented in a data storage device, a communication system (e.g., a wireless communication device or a wired communication device), or another electronic device.Type: ApplicationFiled: May 7, 2015Publication date: November 10, 2016Inventors: XINMIAO ZHANG, ITAI DROR
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Patent number: 9246511Abstract: A method includes, in a data storage device, determining an estimated compression ratio. The estimated compression ratio is based on hash values of a subset of a data set. The method includes selectively processing the data set based on the estimated compression ratio prior to storage of data associated with the data set in a memory of the data storage device.Type: GrantFiled: March 20, 2012Date of Patent: January 26, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventors: Alon Kipnis, Itai Dror
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Patent number: 9244765Abstract: A memory device (e.g., a flash memory device) includes power efficient codeword error analysis circuitry. The circuitry analyzes codewords stored in the memory of the memory device to locate and correct errors in the codewords before the codewords are communicated to a host device that requests the codewords from the memory device. The circuitry includes a highly parallel configuration with reduced complexity (e.g., reduced gate count) that a controller may cause to perform the error analysis under most circumstances. The circuitry also includes an analysis section of greater complexity with a less parallel configuration that the controller may cause to perform the error analysis less frequently. Because the more complex analysis section runs less frequently, the error analysis circuitry may provide significant power consumption savings in comparison to prior designs for error analysis circuitry.Type: GrantFiled: December 29, 2011Date of Patent: January 26, 2016Assignee: SanDisk IL Ltd.Inventor: Itai Dror
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Patent number: 9071269Abstract: A data storage device includes a memory and a controller. A method performed in the data storage device includes performing a first transformation of a unit of data to generate a first transformed unit of data. Performing the first transformation includes sorting permutations of the unit of data. The method includes performing a move-to-front transformation of the first transformed unit of data to generate a second transformed unit of data. The method includes performing a weight-based encoding of the second transformed unit of data to generate an encoded unit of data. The encoded unit of data has a same number of bits as the unit of data.Type: GrantFiled: October 1, 2012Date of Patent: June 30, 2015Assignee: SANDISK TECHNOLOGIES INC.Inventors: Alon Kipnis, Itai Dror
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Publication number: 20150178310Abstract: A method performed in a host device includes receiving an input based on a user-visible code associated with a data storage device. The user-visible code corresponds to an identifier of the data storage device. The method includes sending first data associated with the identifier to a server via a network and receiving, from the server at a first time, a copy of second data identifying content stored in the data storage device. The second data is stored in a network-based storage device associated with the server. The method includes displaying, via a user interface of the host device, an indication of the content of the data storage device to enable the content of the data storage device to be identified at the host device independently of whether the data storage device is coupled to the host device.Type: ApplicationFiled: January 15, 2014Publication date: June 25, 2015Applicant: SANDISK TECHNOLOGIES INC.Inventors: MICHAEL FELLNER, ITAI DROR
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Publication number: 20150154109Abstract: A memory system comprising a non-volatile memory and a controller in communication with the non-volatile memory is disclosed. The controller may include a central processing unit (“CPU”) and an internal cache in communication with the CPU via a plurality of cache lines. The CPU is configured to utilize a first subset of the plurality of cache lines when accessing data stored in the internal cache at a first resolution. Additionally, the CPU is configured to utilize a second subset of the plurality of cache lines when accessing data stored in the internal case at a second resolution, where the first and second resolutions are different resolutions.Type: ApplicationFiled: December 3, 2013Publication date: June 4, 2015Applicant: SanDisk Technologies Inc.Inventors: Mark Fiterman, Yoav Weinberg, Itai Dror
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Patent number: 9037779Abstract: Systems and methods for performing wear leveling are disclosed. In one implementation, a controller partitions a memory block into at least a first partition and a second partition. The controller utilizes the first partition of the memory block for storage of data blocks until the first partition reaches a first end of life condition. After the first partition reaches the first end of life condition, the controller utilizes the first partition for storage of data blocks associated with a compression ratio that is less than a compression threshold until the first portion reaches a second end of life condition. The controller additionally utilizes the second partition for the storage of data blocks until the second partition reaches the first end of life condition.Type: GrantFiled: December 19, 2011Date of Patent: May 19, 2015Assignee: SanDisk Technologies Inc.Inventors: Itai Dror, Alon Kipnis
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Patent number: 9006000Abstract: A semiconductor device, such as a semiconductor die, is disclosed including embedded temperature sensors for scanning the junction temperature, Tj, at one or more locations of the semiconductor die while the die is operating. Once a temperature of a hot spot is detected that is above a temperature specified for the die or package containing the die, the die/package may be discarded. Alternatively, the functionality of the die may be altered in a way that reduces the temperature of the hot spots.Type: GrantFiled: May 3, 2012Date of Patent: April 14, 2015Assignee: SanDisk Technologies Inc.Inventors: Deny Hanan, Eddie Redmard, Itai Dror
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Patent number: 8751855Abstract: A method and memory device for generating a time estimate are provided. In one embodiment, a memory device generates a time estimate from time stamps in file system metadata for a plurality of files stored in the memory device and uses the time estimate to perform a time-based activity in the memory device. In another embodiment, a memory device generates a time estimate from time stamps stored in a plurality of files stored in the memory device and uses the time estimate to perform a time-based activity in the memory device. In yet another embodiment, a memory device obtains a plurality of time stamps, selects one or more of the plurality of time stamps based on validity rankings, generates a time estimate from the selected time stamp(s), and uses the time estimate to perform a time-based activity in the memory device.Type: GrantFiled: April 15, 2013Date of Patent: June 10, 2014Assignee: SanDisk IL Ltd.Inventors: Rahav Yairi, Itzhak Pomerantz, Itai Dror, Ori Stern
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Patent number: 8744073Abstract: A system for random number generation includes a digital oscillator circuit, which has a set of available configurations and is operative to generate a random number sequence in accordance with a current configuration selected from the set. The system further includes a randomization circuit, which is operative to produce a pseudo-random stream of values corresponding to the available configurations of the digital oscillator circuit, and to control the digital oscillator circuit to alternate among the available configurations in accordance with the pseudo-random stream of values.Type: GrantFiled: February 25, 2009Date of Patent: June 3, 2014Assignee: SanDisk IL Ltd.Inventors: Itai Dror, Leonid Minz, Boris Dolgunov, Michael Koun
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Publication number: 20140095768Abstract: A data storage device includes a memory and a controller. A method performed in the data storage device includes performing a first transformation of a unit of data to generate a first transformed unit of data. Performing the first transformation includes sorting permutations of the unit of data. The method includes performing a move-to-front transformation of the first transformed unit of data to generate a second transformed unit of data. The method includes performing a weight-based encoding of the second transformed unit of data to generate an encoded unit of data. The encoded unit of data has a same number of bits as the unit of data.Type: ApplicationFiled: October 1, 2012Publication date: April 3, 2014Applicant: SANDISK TECHNOLOGIES INC.Inventors: ALON KIPNIS, ITAI DROR
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Publication number: 20130295697Abstract: A semiconductor device, such as a semiconductor die, is disclosed including embedded temperature sensors for scanning the junction temperature, Tj, at one or more locations of the semiconductor die while the die is operating. Once a temperature of a hot spot is detected that is above a temperature specified for the die or package containing the die, the die/package may be discarded. Alternatively, the functionality of the die may be altered in a way that reduces the temperature of the hot spots.Type: ApplicationFiled: May 3, 2012Publication date: November 7, 2013Inventors: Deny Hanan, Eddie Redmard, Itai Dror
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Publication number: 20130254441Abstract: A method includes, in a data storage device, determining an estimated compression ratio. The estimated compression ratio is based on hash values of a subset of a data set. The method includes selectively processing the data set based on the estimated compression ratio prior to storage of data associated with the data set in a memory of the data storage device.Type: ApplicationFiled: March 20, 2012Publication date: September 26, 2013Applicant: SANDISK TECHNOLOGIES INC.Inventors: ALON KIPNIS, ITAI DROR
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Patent number: 8533564Abstract: A controller coupled to a memory array includes an error correction coding (ECC) engine and an ECC enhancement compression module coupled to the ECC engine. The ECC enhancement compression module is configured to receive and compress control data to be provided to the ECC engine to be encoded. Compressed encoded control data generated at the ECC engine is stored as a codeword at the memory array.Type: GrantFiled: December 23, 2009Date of Patent: September 10, 2013Assignee: Sandisk Technologies Inc.Inventors: Damian Pablo Yurzola, Rajeev Nagabhirava, Arjun Kapoor, Itai Dror
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Patent number: 8533558Abstract: A method includes initiating a compression operation to compress data to be stored in a group of storage elements at a memory device that includes an error correction coding (ECC) engine. The method includes selecting one of a first mode of the ECC engine to generate a first number of parity bits and a second mode of the ECC engine to generate a second number of parity bits based on an extent of compression of the data. The method also includes encoding the compressed data to generate parity bits corresponding to the compressed data and storing the compressed data and the parity bits to the group of storage elements according to a page format that includes a data portion and a parity portion. The compressed data is stored in the data portion and at least some of the parity bits are stored in the parity portion.Type: GrantFiled: November 29, 2010Date of Patent: September 10, 2013Assignee: Sandisk Technologies Inc.Inventors: Damian Pablo Yurzola, Rajeev Nagabhirava, Arjun Kapoor, Itai Dror, Annie Chi-San Chang, Peter Hwang, Jian Chen
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Publication number: 20130232308Abstract: A method and memory device for generating a time estimate are provided. In one embodiment, a memory device generates a time estimate from time stamps in file system metadata for a plurality of files stored in the memory device and uses the time estimate to perform a time-based activity in the memory device. In another embodiment, a memory device generates a time estimate from time stamps stored in a plurality of files stored in the memory device and uses the time estimate to perform a time-based activity in the memory device. In yet another embodiment, a memory device obtains a plurality of time stamps, selects one or more of the plurality of time stamps based on validity rankings, generates a time estimate from the selected time stamp(s), and uses the time estimate to perform a time-based activity in the memory device.Type: ApplicationFiled: April 15, 2013Publication date: September 5, 2013Inventors: Rahav Yairi, Itzhak Pomerantz, Itai Dror, Ori Stern
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Publication number: 20130159600Abstract: Systems and methods for performing wear leveling are disclosed. In one implementation, a controller partitions a memory block into at least a first partition and a second partition. The controller utilizes the first partition of the memory block for storage of data blocks until the first partition reaches a first end of life condition. After the first partition reaches the first end of life condition, the controller utilizes the first partition for storage of data blocks associated with a compression ratio that is less than a compression threshold until the first portion reaches a second end of life condition. The controller additionally utilizes the second partition for the storage of data blocks until the second partition reaches the first end of life condition.Type: ApplicationFiled: December 19, 2011Publication date: June 20, 2013Inventors: Itai Dror, Alon Kipnis