Patents by Inventor Itai Feit

Itai Feit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190354155
    Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
    Type: Application
    Filed: July 31, 2019
    Publication date: November 21, 2019
    Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
  • Patent number: 10474216
    Abstract: A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: November 12, 2019
    Assignee: INTEL CORPORATION
    Inventors: Doron Rajwan, Dorit Shapira, Itai Feit, Nadav Shulman, Efraim (Efi) Rotem, Tal Kuzi, Eliezer Weissmann, Tomer Ziv, Nir Rosenzweig
  • Patent number: 10394300
    Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
  • Publication number: 20180314307
    Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
    Type: Application
    Filed: April 30, 2018
    Publication date: November 1, 2018
    Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
  • Patent number: 9996135
    Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
  • Patent number: 9864667
    Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 9, 2018
    Assignee: Intel Corporation
    Inventors: Doron Rajwan, Eliezer Weissmann, Yoni Aizik, Itai Feit, Tal Kuzi, Tomer Ziv, Nadav Shulman
  • Publication number: 20170177065
    Abstract: A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 22, 2017
    Inventors: Doron Rajwan, Dorit Shapira, Itai Feit, Nadav Shulman, Efraim (Efi) Rotem, Tal Kuzi, Eliezer Weissmann, Tomer Ziv, Nir Rosenzweig
  • Publication number: 20170090945
    Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Applicant: Intel Corporation
    Inventors: Doron Rajwan, Eliezer Weissmann, Yoni Aizik, Itai Feit, Tal Kuzi, Tomer Ziv, Nadav Shulman
  • Patent number: 9541949
    Abstract: In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventors: Tal Kuzi, Nadav Shulman, Ofer J. Nathan, Ori Levy, Itai Feit
  • Publication number: 20160259389
    Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
    Type: Application
    Filed: May 18, 2016
    Publication date: September 8, 2016
    Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
  • Patent number: 9367114
    Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: June 14, 2016
    Assignee: Intel Corporation
    Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
  • Publication number: 20160085263
    Abstract: In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 24, 2016
    Inventors: TAL KUZI, NADAV SHULMAN, OFER J. NATHAN, ORI LEVY, ITAI FEIT
  • Patent number: 9074947
    Abstract: In one embodiment, the present invention includes a method for determining if a core of a multicore processor is in a low power state, and if so, estimating a temperature of the core and storing the estimated temperature in a thermal storage area for the first core. By use of this estimated temperature, an appropriate voltage at which to operate the core when it exits the low power state can be determined. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Itai Feit, Tomer Ziv, Doron Rajwan, Nadav Shulman, Alon Naveh
  • Publication number: 20140258760
    Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
  • Publication number: 20130080803
    Abstract: In one embodiment, the present invention includes a method for determining if a core of a multicore processor is in a low power state, and if so, estimating a temperature of the core and storing the estimated temperature in a thermal storage area for the first core. By use of this estimated temperature, an appropriate voltage at which to operate the core when it exits the low power state can be determined. Other embodiments are described and claimed.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 28, 2013
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Itai Feit, Tomer Ziv, Doron Rajwan, Nadav Shulman, Alon Naveh