Patents by Inventor Itai Feit
Itai Feit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11822409Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.Type: GrantFiled: November 1, 2022Date of Patent: November 21, 2023Assignee: Daedauls Prime LLCInventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
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Publication number: 20230069510Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.Type: ApplicationFiled: November 1, 2022Publication date: March 2, 2023Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
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Patent number: 11507167Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.Type: GrantFiled: December 20, 2021Date of Patent: November 22, 2022Assignee: Daedalus Prime LLCInventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
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Publication number: 20220113779Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
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Patent number: 11175712Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.Type: GrantFiled: July 31, 2019Date of Patent: November 16, 2021Assignee: Intel CorporationInventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
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Publication number: 20190354155Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.Type: ApplicationFiled: July 31, 2019Publication date: November 21, 2019Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
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Patent number: 10474216Abstract: A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.Type: GrantFiled: December 16, 2015Date of Patent: November 12, 2019Assignee: INTEL CORPORATIONInventors: Doron Rajwan, Dorit Shapira, Itai Feit, Nadav Shulman, Efraim (Efi) Rotem, Tal Kuzi, Eliezer Weissmann, Tomer Ziv, Nir Rosenzweig
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Patent number: 10394300Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.Type: GrantFiled: April 30, 2018Date of Patent: August 27, 2019Assignee: Intel CorporationInventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
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Publication number: 20180314307Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.Type: ApplicationFiled: April 30, 2018Publication date: November 1, 2018Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
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Patent number: 9996135Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.Type: GrantFiled: May 18, 2016Date of Patent: June 12, 2018Assignee: Intel CorporationInventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
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Patent number: 9864667Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 25, 2015Date of Patent: January 9, 2018Assignee: Intel CorporationInventors: Doron Rajwan, Eliezer Weissmann, Yoni Aizik, Itai Feit, Tal Kuzi, Tomer Ziv, Nadav Shulman
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Publication number: 20170177065Abstract: A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.Type: ApplicationFiled: December 16, 2015Publication date: June 22, 2017Inventors: Doron Rajwan, Dorit Shapira, Itai Feit, Nadav Shulman, Efraim (Efi) Rotem, Tal Kuzi, Eliezer Weissmann, Tomer Ziv, Nir Rosenzweig
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Publication number: 20170090945Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Applicant: Intel CorporationInventors: Doron Rajwan, Eliezer Weissmann, Yoni Aizik, Itai Feit, Tal Kuzi, Tomer Ziv, Nadav Shulman
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Patent number: 9541949Abstract: In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed.Type: GrantFiled: September 22, 2014Date of Patent: January 10, 2017Assignee: Intel CorporationInventors: Tal Kuzi, Nadav Shulman, Ofer J. Nathan, Ori Levy, Itai Feit
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Publication number: 20160259389Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.Type: ApplicationFiled: May 18, 2016Publication date: September 8, 2016Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
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Patent number: 9367114Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.Type: GrantFiled: March 11, 2013Date of Patent: June 14, 2016Assignee: Intel CorporationInventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
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Publication number: 20160085263Abstract: In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed.Type: ApplicationFiled: September 22, 2014Publication date: March 24, 2016Inventors: TAL KUZI, NADAV SHULMAN, OFER J. NATHAN, ORI LEVY, ITAI FEIT
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Patent number: 9074947Abstract: In one embodiment, the present invention includes a method for determining if a core of a multicore processor is in a low power state, and if so, estimating a temperature of the core and storing the estimated temperature in a thermal storage area for the first core. By use of this estimated temperature, an appropriate voltage at which to operate the core when it exits the low power state can be determined. Other embodiments are described and claimed.Type: GrantFiled: September 28, 2011Date of Patent: July 7, 2015Assignee: Intel CorporationInventors: Avinash N. Ananthakrishnan, Efraim Rotem, Itai Feit, Tomer Ziv, Doron Rajwan, Nadav Shulman, Alon Naveh
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Publication number: 20140258760Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Inventors: Ryan D. Wells, Itai Feit, Doron Rajwan, Nadav Shulman, Zeev Offen, Inder M. Sodhi
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Publication number: 20130080803Abstract: In one embodiment, the present invention includes a method for determining if a core of a multicore processor is in a low power state, and if so, estimating a temperature of the core and storing the estimated temperature in a thermal storage area for the first core. By use of this estimated temperature, an appropriate voltage at which to operate the core when it exits the low power state can be determined. Other embodiments are described and claimed.Type: ApplicationFiled: September 28, 2011Publication date: March 28, 2013Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Itai Feit, Tomer Ziv, Doron Rajwan, Nadav Shulman, Alon Naveh