Abstract: A method for error detection and recovery is provided in which a host controller and host software collaborate together. The host controller may: detect an error condition, set an error interrupt or register, and/or halt task execution or processing at the host controller. The host software may: detect an error condition as a result of the host controller having set the error interrupt or register; performs error handling, and clears the error condition. The host controller then resumes execution or processing of tasks upon detecting that error condition has been cleared by the host software.

Abstract: A method for error detection and recovery is provided in which a host controller and host software collaborate together. The host controller may: detect an error condition, set an error interrupt or register, and/or halt task execution or processing at the host controller. The host software may: detect an error condition as a result of the host controller having set the error interrupt or register; performs error handling, and clears the error condition. The host controller then resumes execution or processing of tasks upon detecting that error condition has been cleared by the host software.

Abstract: A host controller is provided that unilaterally supports queue barrier functionality. The host controller may receive a first task marked with a queue barrier indicator. As a result, the host controller stalls transmission of the first task to a target device. Additionally, the host controller also stalls transmission of any task, occurring after the first task, to the target device. The host controller only sends the first task to the target device once an indication is received from the target device that all previously sent tasks have been processed. The host controller only sends any task, occurring after the first task, to the target device once an indication is received from the target device that the first task has been processed.