Abstract: A capacitive amplifier device and technique for mitigating the perturbation within the switchable terminals of a feedback capacitor which is produced by the switching activity performed as part of the device's operation. The capacitive amplifier contains feedback components which can be switched without producing significant kickback or poorly behaved transitions due to the inclusion of at least one dedicated circuit. The dedicated circuit is a kickback limiter circuitry which is connected to a switchable node and is designed to reduce the kickback. The technique for reducing the kickback produced can be achieved by connecting and activating the kickback limiter circuitry.

Abstract: Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.

Abstract: A circuit may include or may be coupled to a precharge structure to reduce or minimize a net perturbation, caused by switching, in the input source. Apparatus and techniques shown herein may enable low input current operation in a signal chain of an analog circuit by such reduction or minimization of such perturbation.

Abstract: Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.

Abstract: A circuit may include or may be coupled to a precharge structure to reduce or minimize a net perturbation, caused by switching, in the input source. Apparatus and techniques shown herein may enable low input current operation in a signal chain of an analog circuit by such reduction or minimization of such perturbation.

Abstract: A switched-capacitor integrator is described having the contribution to offset from the charge injection mismatch of switches connected to the summing nodes mitigated by using a switching scheme that conveys basically all the charge injection to the output, thus preventing net offset from being integrated.

Abstract: A Segmented Voltage Continuous-Time Digital-to-Analog Converter is disclosed which provides the benefits of segmentation while minimizing the associated disadvantages. The segmented digital to analog converter disclosed here features, in particular, inherent monotonicity and low transition glitches. The segmentation technique is based on coupling an array of switchable current sources and at least one current divider into a resistor string, providing, at least, three levels of segmentation.

Abstract: A digital input to a digital-to-analog converter (DAC) is divided into a most significant portion and a lesser significant portion. At least one tap voltage generator generates a plurality of voltages, preferably using a resistor string. A decoder decodes at least one sub-word that forms the lesser significant portion to generate a corresponding at least one control signal. A switching unit accesses voltages generated by the at least one tap voltage generator in response to the at least one control signal. A scaled current generator generates a respective weighted current from each accessed voltage. An output stage combines all the weighted currents with a voltage that is an analog representation of the most significant portion of the digital input to generate an analog approximation of the entire digital input.

Abstract: A digital input to a digital-to-analog converter (DAC) is divided into a most significant portion and a lesser significant portion. At least one tap voltage generator generates a plurality of voltages, preferably using a resistor string. A decoder decodes at least one sub-word that forms the lesser significant portion to generate a corresponding at least one control signal. A switching unit accesses voltages generated by the at least one tap voltage generator in response to the at least one control signal. A scaled current generator generates a respective weighted current from each accessed voltage. An output stage combines all the weighted currents with a voltage that is an analog representation of the most significant portion of the digital input to generate an analog approximation of the entire digital input.