Patents by Inventor Itaru Iida

Itaru Iida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150214088
    Abstract: Disclosed is a pickup method in which a first suction unit is caused to approach and come into contact with a chip adhered to an adhesive sheet, and a second suction unit which is formed with a concavity on a contact surface configured to come into contact with the adhesive sheet is caused to approach and come into contact with the adhesive sheet in such a manner as to be opposite to the first suction unit. The adhesive sheet is sucked by the second suction unit that is in contact with the adhesive sheet, and a fluid is injected between the adhesive sheet and the chip by an injection unit. As a result, the adhesive sheet is detached from a portion of the chip opposite to the concavity, and in the state where the chip is being sucked by the first suction unit, the first suction unit is caused to be spaced away from the adhesive sheet that is being sucked by the second suction unit. In this manner, the chip is detached and picked up from the adhesive sheet.
    Type: Application
    Filed: June 30, 2011
    Publication date: July 30, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Ken Nakao, Michikazu Nakamura, Itaru Iida, Muneo Harada
  • Publication number: 20140239484
    Abstract: In a method for forming a sintered silver coating film, for use as a heat spreader, on a semiconductor substrate or a semiconductor package, a coating film of an ink or paste containing silver nanoparticles is formed on one surface of the semiconductor substrate or the substrate package. Further, the coating film is sintered by heating the coating film under an atmosphere of a humidity of 30% to 50% RH (30° C.) by a ventilation oven.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 28, 2014
    Applicant: Tokyo Electron Limited
    Inventors: Kenji MATSUDA, Dai SHINOZAKI, Muneo HARADA, Yoshinobu MITANO, Michikazu NAKAMURA, Itaru IIDA, Shinjiro WATANABE
  • Patent number: 8546185
    Abstract: Provided is a method for manufacturing a semiconductor device which includes: providing a plurality of semiconductor substrates formed with through holes which penetrate between main surfaces of the substrates and are filled with porous conductors; stacking the plurality of semiconductor substrates while aligning the porous conductors filled in the through holes; introducing conductive ink containing particle-like conductors into the porous conductors of the plurality of stacked semiconductor substrates; and sintering the plurality of stacked semiconductor substrates.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: October 1, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Ken Nakao, Muneo Harada, Itaru Iida, Eiji Yamaguchi
  • Publication number: 20120252164
    Abstract: Provided is a method for manufacturing a semiconductor device which includes: providing a plurality of semiconductor substrates formed with through holes which penetrate between main surfaces of the substrates and are filled with porous conductors; stacking the plurality of semiconductor substrates while aligning the porous conductors filled in the through holes; introducing conductive ink containing particle-like conductors into the porous conductors of the plurality of stacked semiconductor substrates; and sintering the plurality of stacked semiconductor substrates.
    Type: Application
    Filed: February 17, 2012
    Publication date: October 4, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Ken NAKAO, Muneo HARADA, Itaru IIDA, Eiji YAMAGUCHI
  • Patent number: 6380753
    Abstract: A power supply applies a power supply voltage to a large number of devices formed on a wafer W. In the state where the devices are quiescent, the quiescent power supply currents flowing through them are measured. If measurements are greater than a setting value, the corresponding devices are determined to be defective. A cutoff circuit prevents voltage application to such defective devices. After this preliminary test, an IDDQ test, an AC test, a DC test and a function test are executed. These tests are executed not by a control station but by an application/measurement module provided for a prober.
    Type: Grant
    Filed: March 8, 1999
    Date of Patent: April 30, 2002
    Assignee: Tokyo Electron Limited
    Inventors: Shinji Iino, Itaru Iida
  • Patent number: 6268740
    Abstract: A test system of the present invention is suitable especially for a reliability test. A reader (23) for reading a wafer identification code attached to a wafer (W) and a reader (24) for reading a shell identification code (14) attached to a test shell (1), are provided for an aligner (2). A reader (36) for reading the shell identification code (14) is provided for a rest apparatus. A transmission system (41) is provided, through which information read by the readers (24, 36) are exchanged between the aligner (2) and the test apparatus (3). A storage devices (25b, 34b, 35b) are used for storing the information. Owing to the use of these structural elements, the IC chips formed on a semiconductor wafer can be accurately tested with high efficiency. The test shell used in the test can be disassembled accurately and reliably.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: July 31, 2001
    Assignee: Tokyo Electron Limited
    Inventor: Itaru Iida
  • Patent number: 5691764
    Abstract: A probe apparatus incorporated into a lighting inspection system for LCD panels, includes a store section, a process section, and a transfer section interposed between them. An examination mechanism having a probe card is arranged in an examination area of the process section. Right and left alignment areas are formed so as to interpose the examination area, and right and left work tables on which the LCD panels are to be loaded, are arranged on the right and left alignment areas, respectively. The movement of the right and left work tables is controlled by a controller, and the LCD panels on the right and left work tables are alternately examined in the examination area by the examination mechanism.
    Type: Grant
    Filed: August 3, 1995
    Date of Patent: November 25, 1997
    Assignee: Tokyo Electron Limited
    Inventors: Kiyoshi Takekoshi, Shinji Iino, Itaru Iida
  • Patent number: 5568054
    Abstract: A probe apparatus having a burn-in test function includes an apparatus body, a probe card, having a plurality of probes, for causing the plurality of probes to electrically contact a semiconductor wafer, a tester for measuring the electrical characteristics of the semiconductor wafer, heating and cooling mechanisms for applying a thermal stress to test target chips, as targets of the burn-in test, of the semiconductor wafer, and an electrical mechanism for applying an electrical stress to the chips.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: October 22, 1996
    Assignees: Tokyo Electron Limited, Tokyo Electron Yamanashi Limited
    Inventors: Shinji Iino, Itaru Iida