Patents by Inventor Itaru Inoue

Itaru Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6457158
    Abstract: In a method for placing an electrode for signal observation, after tracking equipotential wires, conducting the collation to give the correspondence in connection relation and adding the wire name to the collated wire, it is checked out whether the top-layer wire exists about all equipotential wires, if the equipotential wire connected to the top-layer wire exists, the concerned wire name and top-layer wire information are extracted and output. If the equipotential wire connected to the top-layer wire does not exist, it is judged whether the lead-out to the top layer of equipotential wire is possible or not in cases of moving the wire and not moving the wire, then, according to the result, a given processing is conducted. Thus, the placement position of electrode on chip to equipotential wire desired to conduct the signal observation is searched automatically.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: September 24, 2002
    Assignee: NEC Corporation
    Inventor: Itaru Inoue
  • Publication number: 20010054904
    Abstract: A monitoring resistor element includes a plurality of resistors (1, 2) formed on an integrated circuit chip through the same fabrication steps as those used to form a practical circuit are connected to power source pads (3, 4, 5, 6), which are terminal pads formed on the integrated circuit chip. A method for measuring a relative preciseness of resistors (1, 2) formed on an integrated circuit chip includes the step of performing the relative preciseness of the resistors by using power source pads (3, 4, 5, 6), to which the resistors (1, 2) are connected and which are terminal pads formed on the integrated circuit chip, as measuring pads when the measurement of relative preciseness of the resistors (1, 2) is performed.
    Type: Application
    Filed: May 30, 2001
    Publication date: December 27, 2001
    Inventor: Itaru Inoue
  • Patent number: 5923048
    Abstract: A semiconductor integrated circuit device is provided, which is capable of further reduction in chip size without raising any bad effect to the function of the device, and deletion of the TEG region. A test element is formed on a semiconductor substrate. An insulating layer is formed on or over the substrate to cover the test element. An internal circuitry is formed on the substrate. A bonding pad is formed on the insulating layer. The test element is entirely or partially overlapped with the overlying bonding pad. The bonding pad includes a first part and a second part electrically insulated from each other. The first part of the bonding pad is electrically connected to the internal circuitry. The second part of the bonding pad is electrically connected to a terminal of the test element. On a verification test, one of the probes of a tester is contacted with the second part of the bonding pad, and another one thereof is contacted with the first part or an additional part thereof.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: July 13, 1999
    Assignee: NEC Corporation
    Inventor: Itaru Inoue
  • Patent number: 5266416
    Abstract: An aluminum-stabilized superconducting wire includes a superconducting wire member obtained by burying a superconducting filament in a copper matrix and an aluminum stabilizing member covered in an outer surface of the superconducting wire member, and the aluminum stabilizing member is constituted by an aluminum alloy having a 0.2 % proof resistivity of 4 kg/mm.sup.2 or more at a very low temperature and a residual resistance ratio of 250 or more. It is preferable that the aluminum alloy contains at least one element selected from 50 to 1,000 ppm of Zn, 50 to 150 ppm of Si, 50 to 400 ppm of Ag, 50 to 300 ppm of Cu, and 30 to 2,000 ppm of Ce, and that a balance is constituted by Al and an inevitable impurity.
    Type: Grant
    Filed: February 11, 1992
    Date of Patent: November 30, 1993
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Itaru Inoue, Yoshinori Nagasu, Keizo Kosugi, Takuya Suzuki