Patents by Inventor Itaru Tamura

Itaru Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818656
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, second, third and fourth semiconductor regions of a second conductivity type, a first insulating film, a second insulating film, a first electrode contacting the first insulating film, and a second electrode contacting the second insulating film. The second and third semiconductor regions contact the first semiconductor region. The fourth semiconductor region contacts the first semiconductor region, is disposed between the second semiconductor region and the third semiconductor region. The first insulating film contacts a first portion of the first semiconductor region between the second semiconductor region and the fourth semiconductor region. The second insulating film contacts a second portion of the first semiconductor region between the third semiconductor region and the fourth semiconductor region. The second insulating film is thicker than the first insulating film.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 27, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hidekazu Inoto, Osamu Takata, Itaru Tamura, Naozumi Terada, Hiroyoshi Kitahara
  • Publication number: 20200083218
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, second, third and fourth semiconductor regions of a second conductivity type, a first insulating film, a second insulating film, a first electrode contacting the first insulating film, and a second electrode contacting the second insulating film. The second and third semiconductor regions contact the first semiconductor region. The fourth semiconductor region contacts the first semiconductor region, is disposed between the second semiconductor region and the third semiconductor region. The first insulating film contacts a first portion of the first semiconductor region between the second semiconductor region and the fourth semiconductor region. The second insulating film contacts a second portion of the first semiconductor region between the third semiconductor region and the fourth semiconductor region. The second insulating film is thicker than the first insulating film.
    Type: Application
    Filed: March 12, 2019
    Publication date: March 12, 2020
    Inventors: Hidekazu Inoto, Osamu Takata, Itaru Tamura, Naozumi Terada, Hiroyoshi Kitahara
  • Patent number: 9470602
    Abstract: A soft packaged sealed battery is contained in an airtight container. The airtight container is decompressed and images of the surface shape of the sealed battery in the airtight container before and after decompression are captured by a CCD camera or the like. Whether or not airtightness of the sealed battery is maintained is determined based on a change in the captured images, e.g. a change in the surface shape appearing as luminance differences of pixels. By this determination method, highly accurate airtightness determination is realized by eliminating the influence of invisible fine creases on a sealed battery surface.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: October 18, 2016
    Assignee: NISSAN MOTOR CO., LTD.
    Inventors: Takeshi Yasooka, Toshihiko Kamiya, Itaru Tamura, Akira Suzuka, Shunji Noda, Takuya Takatsuka
  • Publication number: 20130141571
    Abstract: A soft packaged sealed battery is contained in an airtight container. The airtight container is decompressed and images of the surface shape of the sealed battery in the airtight container before and after decompression are captured by a CCD camera or the like. Whether or not airtightness of the sealed battery is maintained is determined based on a change in the captured images, e.g. a change in the surface shape appearing as luminance differences of pixels. By this determination method, highly accurate airtightness determination is realized by eliminating the influence of invisible fine creases on a sealed battery surface.
    Type: Application
    Filed: June 15, 2011
    Publication date: June 6, 2013
    Inventors: Takeshi Yasooka, Toshihiko Kamiya, Itaru Tamura, Akira Suzuka, Shunji Noda, Takuya Takatsuka
  • Publication number: 20050110151
    Abstract: A semiconductor device uses a low-dielectric-constant film whose dielectric constant k is 3.0 or lower for an interlayer film. The semiconductor device includes a suppression mechanism unit that suppresses peeling of the interlayer film.
    Type: Application
    Filed: December 29, 2004
    Publication date: May 26, 2005
    Inventors: Itaru Tamura, Katsuya Murakami, Naoto Takebe
  • Patent number: 6740979
    Abstract: First wirings are disposed along a straight line in one row or one column of memory cell arrays. A second wiring is disposed above the first wirings and transmits a signal from one end of the second wiring to the other end thereof. Contact plugs connect the first wirings and the second wiring to each other. The first wirings are connected to a plurality of successive memory cells among all the memory cells in the row or column to which the first wirings belong. In case such an LSI is manufactured and defect analysis is made to thereby form an FBM, it is decided that the contact plugs connecting the first wirings to the second wiring are disconnected when a plurality of successive memory cells in one row or one column. Thus, a plurality of defects are expressed by the use of different categories.
    Type: Grant
    Filed: July 8, 1999
    Date of Patent: May 25, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Itaru Tamura
  • Patent number: 6710393
    Abstract: A failure analyzing method using a failure-analyzing semiconductor device includes a first step of manufacturing a semiconductor device adapted for product in predetermined numbers during a first interval and a second step of manufacturing a failure-analyzing semiconductor device in predetermined numbers every second interval during the first interval. The first step includes a step of forming memory cells in a first semiconductor substrate. The second step includes a step of forming memory cells in a second semiconductor substrate and a step of forming first and second digitated interconnections at the same level above the second semiconductor substrate, which are connected to the memory cells and arranged so that the fingers of each of the first and second interconnections are interleaved with those of the other with a predetermined space therebetween.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: March 23, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Itaru Tamura
  • Publication number: 20010005329
    Abstract: A failure analyzing method using a failure-analyzing semiconductor device includes a first step of manufacturing a semiconductor device adapted for product in predetermined numbers during a first interval and a second step of manufacturing a failure-analyzing semiconductor device in predetermined numbers every second interval during the first interval. The first step includes a step of forming memory cells in a first semiconductor substrate. The second step includes a step of forming memory cells in a second semiconductor substrate and a step of forming first and second digitated interconnections at the same level above the second semiconductor substrate, which are connected to the memory cells and arranged so that the fingers of each of the first and second interconnections are interleaved with those of the other with a predetermined space therebetween.
    Type: Application
    Filed: December 28, 2000
    Publication date: June 28, 2001
    Inventor: Itaru Tamura
  • Patent number: 6132535
    Abstract: Provided is a process for improving alloy properties which can improve the high-temperature ductility of a Ni-base heat-resisting alloy while maintaining its excellent high-temperature strength and weldability.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: October 17, 2000
    Assignees: Mitsubishi Heavy Industries, Ltd., Mitsubishi Steel Mfg. Co., Ltd.
    Inventors: Ikuo Okada, Taiji Torigoe, Hisataka Kawai, Koji Takahashi, Itaru Tamura, Shyuichi Sakashita
  • Patent number: 5921309
    Abstract: A production process of a wax pattern having a core, which is used for casting a product having a complicated hollow portion, comprising the steps of: producing two or more wax shells each having a contour of an external surface of a desired casting; and combining the wax shells with a core to obtain a wax pattern having a hollow portion between the wax shells and the core. Using the method, the occurrence of breakage of the core during dewaxing or production of the pwax pattern is extremely reduced, and a lowering in yield rate due to the breakage of the core is remarkably ameliorated.
    Type: Grant
    Filed: October 2, 1997
    Date of Patent: July 13, 1999
    Assignee: Mitsubishi Steel Mfg. Co., Ltd.
    Inventors: Masakatsu Nishida, Koji Sassa, Tsuyoki Kokubun, Akio Ishida, Itaru Tamura
  • Patent number: 5882586
    Abstract: A heat-resistant nickel-based alloy having excellent welding properties, said nickel-based alloy consisting essentially of, in terms of wt. %, 0.05 to 0.25% of C, 18 to 25% of Cr, 15 to 25% of Co, at least one selected from the group consisting of up to 3.5% of Mo and 5 to 10% of W, with W+1/2Mo being 5 to 10%, 1.0 to 5.0% of Ti, 1.0 to 4.0% of Al, 0.5 to 4.5% of Ta, 0.2 to 3.0% of Nb, 0.005 to 0.10% of Zr, 0.001 to 0.01% of B and the balance being Ni and unavoidable impurities, wherein the (Al+Ti) content and the (W+1/2Mo) content are within the range surrounded by the lines connecting points A (Al+Ti: 5%, W+1/2Mo: 10%), B (Al+Ti: 5%, W+1/2Mo: 5%), C (Al+Ti: 7%, W+1/2Mo: 5%), and D (Al+Ti: 7%, W+1/2Mo: 10%) excluding the line A-B in FIG. 1.
    Type: Grant
    Filed: July 24, 1997
    Date of Patent: March 16, 1999
    Assignees: Mitsubishi Steel Mfg. Co., Ltd., Mitsubishi Jukogyo Kabushiki Kaisha
    Inventors: Itaru Tamura, Kazunori Tokoro, Takashi Kawabata, Tsuyoki Kokubun, Toshio Mochizuki, Shuichi Sakashita, Hisataka Kawai, Ikuo Okada, Ichiro Tsuji, Kouji Takahashi, Taiji Torigoe
  • Patent number: 5365458
    Abstract: A motor eccentricity measuring apparatus is provided comprising a detecting device for detecting a deflection of the rotating shaft of a motor, a first, a second, and a third hold device for holding detected values supplied from the detecting device, and an amplifier device for amplifying a difference between two outputs of the first and the second hold device. In operation, RRO is calculated, during a first measuring period, from the detected values of the first and third hold device and NRRO is calculated, during a second measuring period, from the detected values of the first and second hold device and simultaneously, amplified with the amplifier device.
    Type: Grant
    Filed: March 25, 1992
    Date of Patent: November 15, 1994
    Assignee: Nippon Densan Corporation
    Inventors: Itaru Tamura, Akira Toyama