Patents by Inventor Itaru Tsuge

Itaru Tsuge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Therapeutic or prophylactic composition for TDP-43 proteinopathy
    Patent number: 10612021
    Abstract: The present invention aims to provide a composition for the prevention or treatment of TDP-43 proteinopathy using a microRNA targeting the TDP-43 gene. A prophylactic or therapeutic composition for TDP-43 proteinopathy, comprising: one or more nucleic adds selected from the group consisting of isolated RNAs and isolated nucleic acids encoding the RNAs, wherein the RNAs consist of human miR-33 represented by SEQ ID NO: 1, variants of the human miR-33 having one or more mutations, and precursors of the human miR-33 and the variants.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: April 7, 2020
    Assignee: KYOTO UNIVERSITY
    Inventors: Haruhisa Inoue, Itaru Tsuge, Koh Ono, Shigehiko Suzuki, Motoko Naitoh
  • Therapeutic or prophylactic composition for TDP-43 proteinopathy
    Publication number: 20170226508
    Abstract: The present invention aims to provide a composition for the prevention or treatment of TDP-43 proteinopathy using a microRNA targeting the TDP-43 gene. A prophylactic or therapeutic composition for TDP-43 proteinopathy, comprising: one or more nucleic adds selected from the group consisting of isolated RNAs and isolated nucleic acids encoding the RNAs, wherein the RNAs consist of human miR-33 represented by SEQ ID NO: 1, variants of the human miR-33 having one or more mutations, and precursors of the human miR-33 and the variants.
    Type: Application
    Filed: December 6, 2016
    Publication date: August 10, 2017
    Inventors: Haruhisa INOUE, Itaru TSUGE, Koh ONO, Shigehiko SUZUKI, Motoko NAITOH
  • Semiconductor integrated circuit with redundant circuit replacement
    Patent number: 4752914
    Abstract: A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion and for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit for detecting coincidence between data read from the memory unit and a received input address. Data produced from the comparison by the comparison unit is delivered through an external connection terminal.
    Type: Grant
    Filed: May 30, 1985
    Date of Patent: June 21, 1988
    Assignee: Fujitsu Limited
    Inventors: Masao Nakano, Yoshihiro Takemae, Tomio Nakano, Takeo Tatematsu, Junji Ogawa, Takashi Horii, Yasuhiro Fujii, Kimiaki Sato, Norihisa Tsuge, Itaru Tsuge, Sachie Tsuge