Abstract: According to one embodiment, a semiconductor memory device includes a plurality of stacked first chips and a second chip. The second chip outputs a first signal to the first chips. The first chip outputs status information at timing based on the received first signal. The first chip shifts the received first signal and outputs the shifted first signal to the first chip of a next stage in synchronization with the first clock signal. The second chip receives a plurality of status information output in a serial manner from the first chips.

Abstract: According to one embodiment, electrodes are provided in stacked M (M is an integer of 2 or more) semiconductor chips, a transmission units are provided for the semiconductor chips and, based on a chip identification information on a semiconductor chip in the present stage, transmits the chip identification information on a semiconductor chip in the next stage via the electrodes, or transmit a data for setting the chip identification information, and the direction in which an external signal is sent via the electrodes is opposite to the direction in which the chip identification information is transmitted via the electrodes.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of stacked first chips and a second chip. The second chip outputs a first signal to the first chips. The first chip outputs status information at timing based on the received first signal. The first chip shifts the received first signal and outputs the shifted first signal to the first chip of a next stage in synchronization with the first clock signal. The second chip receives a plurality of status information output in a serial manner from the first chips.

Abstract: According to one embodiment, electrodes are provided in stacked M (M is an integer of 2 or more) semiconductor chips, a transmission units are provided for the semiconductor chips and, based on a chip identification information on a semiconductor chip in the present stage, transmits the chip identification information on a semiconductor chip in the next stage via the electrodes, or transmit a data for setting the chip identification information, and the direction in which an external signal is sent via the electrodes is opposite to the direction in which the chip identification information is transmitted via the electrodes.

Abstract: The invention relates to a cholinesterase activator comprising, as an active ingredient, a compound represented by the following general formula (I): ##STR1## wherein A means a group such as a phenyl group or indanyl group, B denotes a group such as a prolyl group or thioprolyl group, and m stands for an integer of 0-5.The cholinesterase activator according to the invention has a strongly activating action on cholinesterase, in particular, a selectively activating action on peripheral cholinesterase and is also high in safety. It is hence useful as an agent for preventing and treating the side effects of central cholinesterase inhibitors, in particular, hepatopathy, and an agent for preventing and treating the side effects of various medicines manifested on the basis of a cholinesterase-inhibiting action.