Abstract: A memory device includes a memory, a secure-access circuit, a plain-access circuit, and protection hardware. The memory includes at least a secure-storage partition assigned a first address range and a plain-storage partition assigned a second address range, disjoint from the first address range. The secure-access circuit is configured to access the secure-storage partition by generating addresses in the first address range. The plain-access circuit is configured to access the plain-storage partition by generating addresses in the second address range. The protection hardware is configured to prevent the plain-access circuit from accessing the first address range assigned to the secure-storage partition.

Abstract: A memory device includes a memory, a secure-access circuit, a plain-access circuit, and protection hardware. The memory includes at least a secure-storage partition assigned a first address range and a plain-storage partition assigned a second address range, disjoint from the first address range. The secure-access circuit is configured to access the secure-storage partition by generating addresses in the first address range. The plain-access circuit is configured to access the plain-storage partition by generating addresses in the second address range. The protection hardware is configured to prevent the plain-access circuit from accessing the first address range assigned to the secure-storage partition.

Abstract: A method for Serial Peripheral Interface (SPI) operating-mode synchronization between an SPI host and an SPI device, which communicate over an SPI bus, includes predefining, in the SPI device, one or more values on the SPI bus as indicative of lack of synchronization of an SPI operating mode between the SPI host and the SPI device. Re-synchronization of the SPI operating mode is initiated in response to receiving any of the predefined values in the SPI device.

Abstract: A method for Serial Peripheral Interface (SPI) operating-mode synchronization between an SPI host and an SPI device, which communicate over an SPI bus, includes predefining, in the SPI device, one or more values on the SPI bus as indicative of lack of synchronization of an SPI operating mode between the SPI host and the SPI device. Re-synchronization of the SPI operating mode is initiated in response to receiving any of the predefined values in the SPI device.

Abstract: A memory device includes a non-volatile memory (NVM) and circuitry. The circuitry is configured to initialize and prepare the NVM for executing memory-access operations for a processor, and to ascertain that no memory-access operations are received from the processor before the NVM is ready, by preventing the processor from bootstrapping during at least part of initialization and preparation of the NVM.

Abstract: A memory device includes a non-volatile memory (NVM) and circuitry. The circuitry is configured to initialize and prepare the NVM for executing memory-access operations for a processor, and to ascertain that no memory-access operations are received from the processor before the NVM is ready, by preventing the processor from bootstrapping during at least part of initialization and preparation of the NVM.

Abstract: A secured storage system includes a non-volatile memory and a controller. The non-volatile memory is configured to store a first data item and a respective first version identifier assigned to the first data item. The controller is configured to receive a second data item accompanied by a second version identifier and a signature, for replacing the first data item in the non-volatile memory, to authenticate at least the second version identifier using the signature, to make a comparison between the stored first version identifier and the second version identifier, and to replace the first data item with the second data item only in response to verifying that (i) the second version identifier is authenticated successfully, and (ii) the second data item is more recent than the first data item, as indicated by the comparison between the stored first version identifier and the authenticated second version identifier.

Abstract: A memory system includes an interface, a non-volatile memory and a controller. The interface is configured to communicate over an unsecured communication link with an external host. The non-volatile memory is pre-programmed with a device identifier and a corresponding initialization key that are additionally stored in a database that resides externally to the memory system, and is securely accessible by the host. The controller is configured to send the device identifier to the host, to receive from the host, via the interface, binding information that was generated in the host, to generate, using at least the received binding information and the pre-programmed initialization key, a first binding key that matches a second binding key that is generated in the host based on an initialization key securely obtained by the host from the database, and to securely communicate with the host over the communication link using the first binding key.

Abstract: A memory system includes an interface, a non-volatile memory and a controller. The interface is configured to communicate over an unsecured communication link with an external host. The non-volatile memory is pre-programmed with a device identifier and a corresponding initialization key that are additionally stored in a database that resides externally to the memory system, and is securely accessible by the host. The controller is configured to send the device identifier to the host, to receive from the host, via the interface, binding information that was generated in the host, to generate, using at least the received binding information and the pre-programmed initialization key, a first binding key that matches a second binding key that is generated in the host based on an initialization key securely obtained by the host from the database, and to securely communicate with the host over the communication link using the first binding key.

Abstract: A secured storage system includes a non-volatile memory and a controller. The non-volatile memory is configured to store a first data item and a respective first version identifier assigned to the first data item. The controller is configured to receive a second data item accompanied by a second version identifier and a signature, for replacing the first data item in the non-volatile memory, to authenticate at least the second version identifier using the signature, to make a comparison between the stored first version identifier and the second version identifier, and to replace the first data item with the second data item only in response to verifying that (i) the second version identifier is authenticated successfully, and (ii) the second data item is more recent than the first data item, as indicated by the comparison between the stored first version identifier and the authenticated second version identifier.

Abstract: The present disclosure is directed to a system and method for performing out-of-order message filtering with aging. The system and method can be used in a destination device that can receive messages out-of-order (i.e., in a different order than they were transmitted) from a source device. The system and method can filter-out or flag for appropriate handling these messages received out-of-order. To perform the above noted message filtering functionality, the system and method uses a database constructed from a content-addressable memory (CAM) and a random-access memory (RAM) to respectively remember source identifiers and sequence identifiers associated with previously received messages. A source identifier identifies the source of a message, and a sequence identifier identifies the transmission order of the message among the messages transmitted from the particular source. Each message can include a source identifier and a corresponding sequence identifier.

Abstract: The present disclosure is directed to a system and method for performing out-of-order message filtering with aging. The system and method can be used in a destination device that can receive messages out-of-order (i.e., in a different order than they were transmitted) from a source device. The system and method can filter-out or flag for appropriate handling these messages received out-of-order. To perform the above noted message filtering functionality, the system and method uses a database constructed from a content-addressable memory (CAM) and a random-access memory (RAM) to respectively remember source identifiers and sequence identifiers associated with previously received messages. A source identifier identifies the source of a message, and a sequence identifier identifies the transmission order of the message among the messages transmitted from the particular source. Each message can include a source identifier and a corresponding sequence identifier.

Abstract: One or more detectors are provided for processing input in parallel with a logic component receiving the same input. Apparatus described herein include one or more logic components that are configured to perform logical operations on an input vector, and one or more detectors that are configured to receive a portion of the input vector. The detector is further configured to perform detections on this portion of the input vector in parallel with the logical operation. Methods described herein include identifying a portion of the input vector, wherein the portion of the input vector appears an output of the logic component, and analyzing the portion of the vector in parallel with a logical operation performed by the logic component.

Abstract: One or more detectors are provided for processing input in parallel with a logic component receiving the same input. Apparatus described herein include one or more logic components that are configured to perform logical operations on an input vector, and one or more detectors that are configured to receive a portion of the input vector. The detector is further configured to perform detections on this portion of the input vector in parallel with the logical operation. Methods described herein include identifying a portion of the input vector, wherein the portion of the input vector appears an output of the logic component, and analyzing the portion of the vector in parallel with a logical operation performed by the logic component.

Abstract: Embodiments of the present invention provide a method, apparatus and system for selectively switching between at least first and second configurations of a carry-save-adder bit slice corresponding to at least first and second respective modes of operation of the bit slice. Other embodiments are described and claimed.