Abstract: Systems, apparatuses, and methods for saving power on a bus interface are described. A system includes a host, a device, and a repeater interposed between the host and the device. While the host and device are in a low-power state, the repeater monitors a first bus to determine if the device has woken up. When the repeater detects a remote wake-up event initiated by the device, the repeater generates an interrupt which is sent to the host. The host responds to the interrupt by initiating a resume wake-up event procedure that assumes the device is still asleep. In this way, the host is able to stay in the low-power state longer while also using a wake-up procedure that does not require the host to be aware of the existence of the repeater.

Abstract: Systems, apparatuses, and methods for saving power on a bus interface are described. A system includes a host, a device, and a repeater interposed between the host and the device. While the host and device are in a low-power state, the repeater monitors a first bus to determine if the device has woken up. When the repeater detects a remote wake-up event initiated by the device, the repeater generates an interrupt which is sent to the host. The host responds to the interrupt by initiating a resume wake-up event procedure that assumes the device is still asleep. In this way, the host is able to stay in the low-power state longer while also using a wake-up procedure that does not require the host to be aware of the existence of the repeater.

Abstract: Systems, apparatuses, and methods for saving power on a bus interface are described. A system includes a host, a device, and a repeater interposed between the host and the device. While the host and device are in a low-power state, the repeater monitors a first bus to determine if the device has woken up. When the repeater detects a remote wake-up event initiated by the device, the repeater generates an interrupt which is sent to the host. The host responds to the interrupt by initiating a resume wake-up event procedure that assumes the device is still asleep. In this way, the host is able to stay in the low-power state longer while also using a wake-up procedure that does not require the host to be aware of the existence of the repeater.

Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

Abstract: Disclosed is an address translation system. The processor includes a first address translator circuit and a second address translator circuit, coupled to a first functional unit and a second functional unit, respectively. The first address translator circuit translates a first original address to a first translated address and the second address translator translates a second original address to a second translated address as first-level address translation services (ATSs). An arbiter circuit is coupled between the first and second address translator circuits and a memory management circuit. The memory management circuit translates addresses as a second-level ATS when requested by at least one of the first address translator circuit or the second address translator circuit.

Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

Abstract: Disclosed is an address translation system. The processor includes a first address translator circuit and a second address translator circuit, coupled to a first functional unit and a second functional unit, respectively. The first address translator circuit translates a first original address to a first translated address and the second address translator translates a second original address to a second translated address as first-level address translation services (ATSs). An arbiter circuit is coupled between the first and second address translator circuits and a memory management circuit. The memory management circuit translates addresses as a second-level ATS when requested by at least one of the first address translator circuit or the second address translator circuit.

Abstract: Disclosed is an address translation system. The processor includes a first address translator circuit and a second address translator circuit, coupled to a first functional unit and a second functional unit, respectively. The first address translator circuit translates a first original address to a first translated address and the second address translator translates a second original address to a second translated address as first-level address translation services (ATSs). An arbiter circuit is coupled between the first and second address translator circuits and a memory management circuit. The memory management circuit translates addresses as a second-level ATS when requested by at least one of the first address translator circuit or the second address translator circuit.

Abstract: Disclosed is an address translation system. The apparatus includes a memory management unit (MMU) that is operable to receive a translation request for an original address and translate the original address to a translated address as a second-level address translation service (ATS). The apparatus also includes an address translator having an associated cache to store the original address and the first translated address. The address translator is to translate memory addresses as a first-level address translation service (ATS). The address translator determines whether the transaction is to be processed using either the first-level ATS or the second-level ATS. The address translator translates a current memory address of the transaction to a current translated address using the first-level ATS or the second-level ATS based on the determination, The address translator also dispatches the transaction with the current translated address to a memory device where it may be further processed.

Abstract: Disclosed is an address translation system. The apparatus includes a memory management unit (MMU) that is operable to receive a translation request for an original address and translate the original address to a translated address as a second-level address translation service (ATS). The apparatus also includes an address translator having an associated cache to store the original address and the first translated address. The address translator is to translate memory addresses as a first-level address translation service (ATS). The address translator determines whether the transaction is to be processed using either the first-level ATS or the second-level ATS. The address translator translates a current memory address of the transaction to a current translated address using the first-level ATS or the second-level ATS based on the determination, The address translator also dispatches the transaction with the current translated address to a memory device where it may be further processed.

Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

Abstract: A mechanism is described for facilitating efficient operations paths for storage devices in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes identifying a request for power mode change at a storage device at a computing system. The request for power mode change indicates potential reduced power state of the storage device. The method may further include transferring context information at the storage device to a host memory at the computing system, in response to the first command, and saving the context information at the host memory, wherein the storage device is at reduced power state.

Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.

Abstract: Embodiments of the present invention may provide a apparatus and method for compressing image data by dividing the data into color components data streams, taking the differences between successive pixels in the data streams, and coding these differences into a compressed data stream using a Huffman coding scheme. The compressed data may be transmitted to a decompressor over an interface. The decompressor may divide the compressed data stream back into color component data streams and decompress the pixels by adding the coded differences to reference values corresponding to previously decompressed pixels of the same color component to generate successive pixels of that color component. Merge registers may then recombined the decompressed data into the original image data. According to embodiments of the present invention, the compression/decompression process may be lossless.

Abstract: A graphics processing system with multiple graphics processing cores (GPC)s is disclosed. The apparatus can include a peripheral component interface express (PCIe) switch to interface the GPCs to a host processor. The apparatus can also include a transparent bus to connect the GPCs. The transparent bus can be implemented with two PCIe endpoints on each side of a nontransparent bridge where these three components provide a bus interconnect and a control line interconnect between the GPCs. Other embodiments are also disclosed.

Abstract: A mechanism is described for facilitating efficient operations paths for storage devices in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes identifying a request for power mode change at a storage device at a computing system. The request for power mode change indicates potential reduced power state of the storage device. The method may further include transferring context information at the storage device to a host memory at the computing system, in response to the first command, and saving the context information at the host memory, wherein the storage device is at reduced power state.

Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.

Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.

Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.