Patents by Inventor Itay Franko

Itay Franko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190065390
    Abstract: Disclosed is an address translation system. The processor includes a first address translator circuit and a second address translator circuit, coupled to a first functional unit and a second functional unit, respectively. The first address translator circuit translates a first original address to a first translated address and the second address translator translates a second original address to a second translated address as first-level address translation services (ATSs). An arbiter circuit is coupled between the first and second address translator circuits and a memory management circuit. The memory management circuit translates addresses as a second-level ATS when requested by at least one of the first address translator circuit or the second address translator circuit.
    Type: Application
    Filed: June 25, 2018
    Publication date: February 28, 2019
    Inventor: Itay Franko
  • Publication number: 20190011976
    Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 13, 2018
    Publication date: January 10, 2019
    Applicant: Intel Corporation
    Inventors: Jawad Haj-Yihia, Eliezer Weissmann, Vijay S. R. Degalahal, Nadav Shulman, Tal Kuzi, Itay Franko, Amit Gur, Efraim Rotem
  • Patent number: 10114448
    Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Jawad Haj-Yihia, Eliezer Weissmann, Vijay S R Degalahal, Nadav Shulman, Tal Kuzi, Itay Franko, Amit Gur, Efraim Rotem
  • Patent number: 10007618
    Abstract: Disclosed is an address translation system. The processor includes a first address translator circuit and a second address translator circuit, coupled to a first functional unit and a second functional unit, respectively. The first address translator circuit translates a first original address to a first translated address and the second address translator translates a second original address to a second translated address as first-level address translation services (ATSs). An arbiter circuit is coupled between the first and second address translator circuits and a memory management circuit. The memory management circuit translates addresses as a second-level ATS when requested by at least one of the first address translator circuit or the second address translator circuit.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: June 26, 2018
    Assignee: Intel Corporation
    Inventor: Itay Franko
  • Publication number: 20170177495
    Abstract: Disclosed is an address translation system. The processor includes a first address translator circuit and a second address translator circuit, coupled to a first functional unit and a second functional unit, respectively. The first address translator circuit translates a first original address to a first translated address and the second address translator translates a second original address to a second translated address as first-level address translation services (ATSs). An arbiter circuit is coupled between the first and second address translator circuits and a memory management circuit. The memory management circuit translates addresses as a second-level ATS when requested by at least one of the first address translator circuit or the second address translator circuit.
    Type: Application
    Filed: March 6, 2017
    Publication date: June 22, 2017
    Inventor: Itay Franko
  • Patent number: 9632948
    Abstract: Disclosed is an address translation system. The apparatus includes a memory management unit (MMU) that is operable to receive a translation request for an original address and translate the original address to a translated address as a second-level address translation service (ATS). The apparatus also includes an address translator having an associated cache to store the original address and the first translated address. The address translator is to translate memory addresses as a first-level address translation service (ATS). The address translator determines whether the transaction is to be processed using either the first-level ATS or the second-level ATS. The address translator translates a current memory address of the transaction to a current translated address using the first-level ATS or the second-level ATS based on the determination, The address translator also dispatches the transaction with the current translated address to a memory device where it may be further processed.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventor: Itay Franko
  • Publication number: 20160085688
    Abstract: Disclosed is an address translation system. The apparatus includes a memory management unit (MMU) that is operable to receive a translation request for an original address and translate the original address to a translated address as a second-level address translation service (ATS). The apparatus also includes an address translator having an associated cache to store the original address and the first translated address. The address translator is to translate memory addresses as a first-level address translation service (ATS). The address translator determines whether the transaction is to be processed using either the first-level ATS or the second-level ATS. The address translator translates a current memory address of the transaction to a current translated address using the first-level ATS or the second-level ATS based on the determination, The address translator also dispatches the transaction with the current translated address to a memory device where it may be further processed.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 24, 2016
    Inventor: Itay Franko
  • Publication number: 20160004296
    Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Applicant: Intel Corporation
    Inventors: JAWADH HAJ-YIHIA, ELIEZER WEISSMANN, VIJAY S R DEGALAHAL, NADAV SHULMAN, TAL KUZI, ITAY FRANKO, AMIT GUR, EFRAIM ROTEM
  • Patent number: 9207749
    Abstract: A mechanism is described for facilitating efficient operations paths for storage devices in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes identifying a request for power mode change at a storage device at a computing system. The request for power mode change indicates potential reduced power state of the storage device. The method may further include transferring context information at the storage device to a host memory at the computing system, in response to the first command, and saving the context information at the host memory, wherein the storage device is at reduced power state.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: December 8, 2015
    Assignee: Intel Corporation
    Inventors: Nimrod Diamant, Ohad Falik, Itay Franko, Robert W. Strong
  • Patent number: 8908688
    Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: December 9, 2014
    Assignee: Intel Corporation
    Inventors: Chih-Cheh Chen, Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo, Mohan K. Nair, Chris Van Beek
  • Publication number: 20140185928
    Abstract: Embodiments of the present invention may provide a apparatus and method for compressing image data by dividing the data into color components data streams, taking the differences between successive pixels in the data streams, and coding these differences into a compressed data stream using a Huffman coding scheme. The compressed data may be transmitted to a decompressor over an interface. The decompressor may divide the compressed data stream back into color component data streams and decompress the pixels by adding the coded differences to reference values corresponding to previously decompressed pixels of the same color component to generate successive pixels of that color component. Merge registers may then recombined the decompressed data into the original image data. According to embodiments of the present invention, the compression/decompression process may be lossless.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Shai Ben NUN, Lior LIBIS, Itay FRANKO
  • Patent number: 8711153
    Abstract: A graphics processing system with multiple graphics processing cores (GPC)s is disclosed. The apparatus can include a peripheral component interface express (PCIe) switch to interface the GPCs to a host processor. The apparatus can also include a transparent bus to connect the GPCs. The transparent bus can be implemented with two PCIe endpoints on each side of a nontransparent bridge where these three components provide a bus interconnect and a control line interconnect between the GPCs. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: April 29, 2014
    Assignee: Intel Corporation
    Inventors: Itay Franko, Anshuman Thakur
  • Publication number: 20140068281
    Abstract: A mechanism is described for facilitating efficient operations paths for storage devices in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes identifying a request for power mode change at a storage device at a computing system. The request for power mode change indicates potential reduced power state of the storage device. The method may further include transferring context information at the storage device to a host memory at the computing system, in response to the first command, and saving the context information at the host memory, wherein the storage device is at reduced power state.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Inventors: Nimrod Diamant, Ohad Falik, Itay Franko, Robert W. Strong
  • Publication number: 20130016720
    Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 17, 2013
    Inventors: Chih-Cheh Chen, Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo, Mohan K. Nair, Christopher Van Beek
  • Patent number: 8270405
    Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: September 18, 2012
    Assignee: Intel Corporation
    Inventors: Chih-Cheh Chen, Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo, Mohan K. Nair, Christopher Van Beek
  • Publication number: 20100329254
    Abstract: Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Applicant: INTEL CORPORATION
    Inventors: Chih-Cheh Chen, Michael T. Klinglesmith, David M. Lee, John Zulauf, Itay Franko, Peter J. Elardo, Mohan K. Nair, Christopher Van Beek
  • Publication number: 20090167771
    Abstract: A graphics processing system with multiple graphics processing cores (GPC)s is disclosed. The apparatus can include a peripheral component interface express (PCIe) switch to interface the GPCs to a host processor. The apparatus can also include a transparent bus to connect the GPCs. The transparent bus can be implemented with two PCIe endpoints on each side of a nontransparent bridge where these three components provide a bus interconnect and a control line interconnect between the GPCs. Other embodiments are also disclosed.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 2, 2009
    Inventors: Itay Franko, Anshuman Thakur