Patents by Inventor Itay Peled
Itay Peled has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170210142Abstract: Printing apparatus (20) includes a donor supply assembly (30), which provides a transparent donor substrate (26) having opposing first and second surfaces and a donor film formed on the second surface so as to position the donor film in proximity a target area (28) on an acceptor substrate (22). An optical assembly (24) directs multiple output beams of laser radiation simultaneously in a predefmed spatial pattern to pass through the first surface of the donor substrate and impinge on the donor film so as to induce ejection of material from the donor film onto the acceptor substrate according, thereby writing the predefined pattern onto the target area of the acceptor substrate.Type: ApplicationFiled: August 2, 2015Publication date: July 27, 2017Inventors: Zvi Kotler, Michael Zenou, Itay Peled
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Publication number: 20170133271Abstract: Aspects of the disclosure provide a method for semiconductor wafer manufacturing. The method includes utilizing a subset of lower level masks in a mask set to form multiple modular units of lower level circuit structures on a semiconductor wafer. The mask set includes the subset of lower level masks and at least a first subset of upper level masks and a second subset of upper level masks. The first subset of upper level masks defines intra-unit interconnections. The second subset of upper level masks defines both intra-unit interconnections and inter-unit interconnections. The method further includes selecting one of at least the first subset of upper level masks and the second subset of upper level masks based on a composition request of a final integrated circuit (IC) product and utilizing the selected subset of upper level masks to form upper level structures on the semiconductor wafer.Type: ApplicationFiled: November 7, 2016Publication date: May 11, 2017Applicant: Marvell Israel (M.I.S.L) Ltd.Inventors: Eran Rotem, Rami Zemach, Itay Peled
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Publication number: 20160188331Abstract: A signal processing device comprising at least one control unit arranged to receive at least one pack-insert instruction, decode the received at least one pack-insert instruction, and output at least one pack-insert control signal in accordance with the received pack-insert instruction. The signal processing device further comprising at least one pack-insert component arranged to receive at least a first data block to be inserted into a sequence of data blocks to be output to at least one destination register, receive a plurality of further data blocks to be packed within the sequence of data blocks to be output to the at least one destination register, arrange the at least first data block and the plurality of further data blocks into a sequence of data blocks based at least partly on the at least one pack-insert control signal, and output the sequence of data blocks.Type: ApplicationFiled: June 18, 2013Publication date: June 30, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Avi GAL, Fabrice AIDAN, Noam ESHEL-GOLDMAN, Roy GLASNER, Dmitry LACHOVER, Itay PELED
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Publication number: 20150215226Abstract: A packet processing system and method for processing data units are provided. A packet processing system includes a processor, first memory having a first latency, and second memory having a second latency that is higher than the first latency. A first portion of a queue for queuing data units utilized by the processor is disposed in the first memory, and a second portion of the queue is disposed in the second memory. A queue manager is configured to push new data units to the second portion of the queue and generate an indication linking a new data unit to an earlier-received data unit in the queue. The queue manager is configured to transfer one or more queued data units from the second portion of the queue to the first portion of the queue prior to popping the queued data unit from the queue, and to update the indication.Type: ApplicationFiled: January 23, 2015Publication date: July 30, 2015Inventors: Itay Peled, Dan Ilan, Michael Weiner, Einat Ophir, Moshe Anschel
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Publication number: 20150149446Abstract: Circuitry for a computing system includes a memory arrangement having at least one memory management unit and at least one processor. The at least one processor is arranged to issue a memory query to the memory management unit. The memory management unit is arranged to provide a query result in response to the memory query directly to the processor via a data connection.Type: ApplicationFiled: July 27, 2012Publication date: May 28, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Ziv Zamsky, Dmitry Flat, Kostantin Godin, Itay Peled
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Patent number: 8886895Abstract: A method for fetching information in response to hazard indication information, the method includes: (i) associating hazard indication information to at least one information unit that is being fetched to the cache module; (ii) receiving a request to perform a fetch operation; and (iii) determining whether to fetch at least one information unit to the cache module in response to the hazard indication information and in response to dirty information associated with the at least one information unit.Type: GrantFiled: September 14, 2004Date of Patent: November 11, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Itay Peled, Moshe Anschel, Jacob Efrat, Alon Eldar, Ziv Zamsky
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Patent number: 8832378Abstract: A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being characterized by including: searching, if the initially selected cache way is locked, for an unlocked cache way, out of at least one group of cache ways that are located at predefined offsets from the first cache way.Type: GrantFiled: April 11, 2008Date of Patent: September 9, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Rotem Porat, Moshe Anschel, Alon Eldar, Amit Gur, Shai Koren, Itay Peled
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Patent number: 8458407Abstract: A method for generating cache user initiated pre-fetch requests, the method comprises initiating a sequence of user initiated pre-fetch requests; the method being characterized by: determining the timing of user initiated pre-fetch requests of the sequence of user initiated pre-fetch requests in response to: the timing of an occurrence of a last triggering event, a user initiated pre-fetch sequence delay period and a user initiated pre-fetch sequence rate.Type: GrantFiled: March 13, 2007Date of Patent: June 4, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Rotem Porat, Moshe Anschel, Shai Koren, Itay Peled, Erez Steinberg
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Patent number: 8117400Abstract: A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from data, wherein the fetch unit is connected to a cache module and to a high level memory unit; determining, when the fetch unit is empty, whether the cache module stores an older version of the information unit; and selectively writing the information unit to the cache module in response to the cache module in response to the determination.Type: GrantFiled: October 20, 2006Date of Patent: February 14, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Ziv Zamsky, Moshe Anschel, Alon Eldar, Dmitry Flat, Kostantin Godin, Itay Peled, Dvir Peleg
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Patent number: 8103833Abstract: A cache memory that includes: (i) an arbitrator, connected to multiple access generator, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle; (ii) a sequence of pipeline stages, the sequence comprises an input pipeline stage that is connected to the arbiter; and (iii) multiple cache resources, connected to the sequence of pipeline stages; wherein each cache resource can be read only by a small portion of the sequence of pipeline stages and can be written to only by a small portion of the sequence of pipeline stages.Type: GrantFiled: September 4, 2007Date of Patent: January 24, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Shai Koren, Alon Eldar, Amit Gur, Itay Peled, Rotem Porat
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Patent number: 8095769Abstract: A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; (iii) wherein a comparison between the input address and a memory segment boundary comprises: (a) applying a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; (b) ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and (c) comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memoType: GrantFiled: August 19, 2008Date of Patent: January 10, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Rotem Porat, Moshe Anschel, Itay Peled, Erez Steinberg, Ziv Zamsky
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Patent number: 8041899Abstract: A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a high level memory unit. A single cache module line includes multiple segments, each segment is adapted to store a single information unit. A content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that includes multiple segment fetch operations. The store request circuit includes a snooper and a controller. The snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst. The controller is adapted to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address.Type: GrantFiled: July 29, 2008Date of Patent: October 18, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Kostantin Godin, Roman Landa, Itay Peled, Yakov Tokar, Ziv Zamsky
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Patent number: 8006015Abstract: A device and a method for managing access requests, the method includes: (i) receiving, from a master component coupled to a master bus, multiple access requests to access a slave component over a pipelined slave bus; acknowledging a received access request if: (a) at least an inter-access request delay period lapsed from a last acknowledgement of an access request; (b) an amount of pending acknowledged access requests is below a threshold; wherein the threshold is determined in response to a pipeline depth of the pipelined slave bus; (c) the received access request is valid; wherein a validity of an access request is responsive to a reception of an access request cancellation request; and (ii) providing information from the slave component, in response to at least one acknowledged access request.Type: GrantFiled: November 8, 2006Date of Patent: August 23, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Yaki Devilla, Moshe Anschel, Kostantin Godin, Amit Gur, Itay Peled
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Publication number: 20110040912Abstract: Apparatus and method for bus matching. The method includes: receiving data transfer characteristics at a first endian mode and at a second endian mode; determining a connectivity of multiple devices to an interfacing bus in response to the data transfer characteristics and in response to a relationship between a width of the interfacing bus and a width of each device interface; wherein at least one device interface is connected in parallel to multiple interfacing bus portions; and configuring a control logic such as to provide control signals representative of a transfer of data over the interfacing bus; whereas the control logic is configured in response to the connectivity.Type: ApplicationFiled: September 10, 2004Publication date: February 17, 2011Applicant: Freescale SemiconductorInventors: Kostantin Godin, Moshe Anschel, Jacob Efrat, Itay Peled, Reuven Badash, Asher Bastaker, Dvir Rune Peleg, Ziv Zamsky
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Publication number: 20110022800Abstract: A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being characterized by including: searching, if the initially selected cache way is locked, for an unlocked cache way, out of at least one group of cache ways that are located at predefined offsets from the first cache way.Type: ApplicationFiled: April 11, 2008Publication date: January 27, 2011Applicant: Freescale Semiconductor, Inc.Inventors: Rotem Porat, Moshe Anschel, Alon Eldar, Amit Gur, Shai Koren, Itay Peled
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Patent number: 7865691Abstract: A virtual address cache and a method for sharing data. The virtual address cache includes: a memory, adapted to store virtual addresses, task identifiers and data associated with the virtual addresses and the task identifiers; and a comparator, connected to the memory, adapted to determine that data associated with a received virtual address and a received task identifier is stored in the memory if at least a portion of the received virtual address equals at least a corresponding portion of a certain stored virtual address and a stored task identifier associated with the certain stored virtual address indicates that the data is shared between multiple tasks.Type: GrantFiled: August 31, 2004Date of Patent: January 4, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Itay Peled, Moshe Anschel, Moshe Bachar, Jacob Efrat, Alon Eldar, Yakov Tokar
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Publication number: 20100325366Abstract: A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from data, wherein the fetch unit is connected to a cache module and to a high level memory unit; determining, when the fetch unit is empty, whether the cache module stores an older version of the information unit; and selectively writing the information unit to the cache module in response to the cache module in response to the determination.Type: ApplicationFiled: October 20, 2006Publication date: December 23, 2010Inventors: Ziv Zamsky, Moshe Anschel, Alon Eldar, Dmitry Flat, Kostantin Godin, Itay Peled, Dvir Peleg
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Publication number: 20100122037Abstract: A method for generating cache user initiated pre-fetch requests, the method comprises initiating a sequence of user initiated pre-fetch requests; the method being characterized by: determining the timing of user initiated pre-fetch requests of the sequence of user initiated pre-fetch requests in response to: the timing of an occurrence of a last triggering event, a user initiated pre-fetch sequence delay period and a user initiated pre-fetch sequence rate.Type: ApplicationFiled: March 13, 2007Publication date: May 13, 2010Applicant: Freescale Semiconductor, Inc.Inventors: Rotem Porat, Moshe Anschel, Shai Koren, Itay Peled, Erez Steinberg
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Patent number: 7716453Abstract: A memory management unit that includes: (i) multiple data segment descriptors, each data segment descriptor associated with a data memory segment; (ii) multiple program segment descriptors, each program segment descriptor associated with a program memory segment; and (iii) a controller, adapted to replace the content of the multiple data segment descriptors and the multiple program segment descriptors in response to a task switch.Type: GrantFiled: September 10, 2004Date of Patent: May 11, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Moshe Anschel, Moshe Bachar, Uri Dayan, Jacob Efrat, Itay Peled, Zvika Rozenshein
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Publication number: 20100049939Abstract: A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; (iii) wherein a comparison between the input address and a memory segment boundary comprises: (a) applying a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; (b) ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and (c) comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memoType: ApplicationFiled: August 19, 2008Publication date: February 25, 2010Inventors: Rotem Porat, Moshe Anschel, Itay Peled, Erez Steinberg, Ziv Zamsky