Abstract: A bond structure is provided. The bond structure includes a seed layer and a conductive structure. The conductive structure includes a via portion over the seed layer and a plurality of wires protruding from the via portion.

Abstract: The present disclosure provides an electronic device and a method of manufacturing the same. The electronic device includes a first redistribution structure and a first encapsulant. The first encapsulant supports the first redistribution structure and is configured to function as a first reinforcement to provide a second redistribution structure. The redistribution structure has a plurality of conductive layers disposed over the first redistribution structure.

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

Abstract: A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.

Abstract: A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.

Abstract: A memory device includes memory includes a multi-layers stack includes a plurality of insulating layers and a plurality conductive layers alternatively stacked on a semiconductor device, a plurality of memory cells formed on the conductive layers, a contact plug passing through the insulating layers and the conductive layers, and a dielectric layer including a plurality of extending parts each of which is inserted between each adjacent two ones of the insulating layers to isolate the conductive layer from the contact plug, wherein any one of the extending parts that has a shorter distance departed from the semiconductor substrate has a size substantially greater than a size of the others that has a longer distance departed from the semiconductor substrate.