Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

Abstract: An apparatus includes a processor and split-read control circuitry (SRCC). The processor is to issue a set of one or more split-read requests for loading one or more data values to one or more respective local registers of the processor. The SRCC is to receive the set of one or more split-read requests, to read the one or more data values on behalf of the processor, and to write the data values into the one or more respective local registers. The processor and the SRCC are to coordinate a status of the split-read requests via a split-read-status indication.

Abstract: An apparatus includes a processor and split-read control circuitry (SRCC). The processor is to issue a set of one or more split-read requests for loading one or more data values to one or more respective local registers of the processor. The SRCC is to receive the set of one or more split-read requests, to read the one or more data values on behalf of the processor, and to write the data values into the one or more respective local registers. The processor and the SRCC are to coordinate a status of the split-read requests via a split-read-status indication.

Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

Abstract: A freezing resistant liquid filter including a housing having a liquid inlet and a liquid outlet and a freezing compensating filter element disposed within the housing and including a folded filter medium having a plurality of interstices and freezing compressible elements located at the interstices.

Abstract: Computational apparatus includes an input buffer configured to hold a first array of input data and an output buffer configured to hold a second array of output data computed by the apparatus. A plurality of processing elements are each configured to compute a convolution of a respective kernel with a set of the input data that are contained within a respective window and to write a result of the convolution to a corresponding location in a respective plane of the output data. One or more data fetch units each read one or more segments of the input data from the input buffer. A shift register delivers the segments of the input data in succession to each of the processing elements in an order selected so that the respective window of each processing element slides in turn over a sequence of window positions covering the first array.

Abstract: A freezing resistant liquid filter including a housing having a liquid inlet and a liquid outlet and a freezing compensating filter element disposed within the housing and including a folded filter medium having a plurality of interstices and freezing compressible elements located at the interstices.

Abstract: A freezing resistant liquid filter including a housing having a liquid inlet and a liquid outlet and a freezing compensating filter element disposed within the housing and including a folded filter medium having a plurality of interstices and freezing compressible elements located at the interstices.

Abstract: A freezing resistant liquid filter including a housing having a liquid inlet and a liquid outlet and a freezing compensating filter element disposed within the housing and including a folded filter medium having a plurality of interstices and freezing compressible elements located at the interstices.