Patents by Inventor Itsumi Sugiyama

Itsumi Sugiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140298126
    Abstract: A latch circuit includes: a data latch that holds data that has been input according to a first control signal or a second control signal; and a latch controller that includes a first input terminal to which a first operation signal is input, the first operation signal operating the data latch in a first scan method, and a second input terminal to which a second operation signal is input, the second operation signal operating the data latch in a second scan method; wherein when a prescribed value is input to the first input terminal, the latch controller outputs the second control signal to control the data latch, and when a prescribed value is input to the second input terminal, the latch controller outputs the first control signal to control the data latch.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 2, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Itsumi Sugiyama
  • Publication number: 20140289578
    Abstract: A scan circuit includes first scan flip-flops each including a first logic circuit to receive a plurality of control signals in addition to a scan input signal and a data input signal, and second scan flip-flops each including a second logic circuit to receive the plurality of control signals in addition to a scan input signal and a data input signal, wherein the first scan flip-flops and the second scan flip-flops are connected in series, and the plurality of control signals include only a one-bit reset signal and control signals whose purpose is other than an initialization purpose, and wherein the plurality of control signals are set to a predetermined combination of logic values to cause each of the first scan flip-flops to be initialized to “0” by the first logic circuit and each of the second scan flip-flops to be initialized to “1” by the second logic circuit.
    Type: Application
    Filed: June 6, 2014
    Publication date: September 25, 2014
    Inventor: Itsumi Sugiyama
  • Patent number: 8350620
    Abstract: An integrated circuit power consumption calculating apparatus obtains power consumption of an integrated circuit by outputting circuit component transistor connection information of each of circuit components after setting a group of transistors connected via a source terminal/drain terminal of a transistor within each cell of an integrated circuit, by outputting circuit component logic model information after extracting a logic for each of the circuit components from the circuit component transistor connection information information, by obtaining power information (circuit component power information) of each signal transition state of an input/output terminal for each of the circuit components based on the circuit component transistor connection information information, by generating signal terminal transition information with a logic simulation performed for each of the circuit components of the integrated circuit, and by obtaining power consumption in a signal transition of an input/output terminal of ea
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Limited
    Inventors: Itsumi Sugiyama, Tomohiro Tanaka
  • Patent number: 8305149
    Abstract: A semiconductor circuit apparatus having a clock oscillating circuit includes a first inverter circuit having a power supply terminal connected to a power supply potential via a first power supply potential connection transistor and a ground terminal connected to a ground potential via a first ground potential connection transistor, an inverter circuit block having a second inverter circuit connected to the power supply potential via a second power supply potential connection transistor and to the ground potential via a second ground potential connection transistor and connected to the first inverter circuit in parallel and a selection circuit block that outputs a power supply potential connection signal to any one of gate terminals of the first and second power supply potential connection transistors and a ground potential connection signal to any one of gate terminals of the first and second ground potential connection transistors.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: November 6, 2012
    Assignee: Fujitsu Limited
    Inventor: Itsumi Sugiyama
  • Publication number: 20120253712
    Abstract: A method of calculating power consumption of an integrated circuit based on circuit information representing an internal configuration of each circuit and connection-between-circuits information is performed by a computer.
    Type: Application
    Filed: June 13, 2012
    Publication date: October 4, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Itsumi SUGIYAMA, Yukihito Kawabe
  • Publication number: 20120249230
    Abstract: An integrated circuit power consumption calculating apparatus obtains power consumption of an integrated circuit by outputting circuit component transistor connection information of each of circuit components after setting a group of transistors connected via a source terminal/drain terminal of a transistor within each cell of an integrated circuit, by outputting circuit component logic model information after extracting a logic for each of the circuit components from the circuit component transistor connection information information, by obtaining power information (circuit component power information) of each signal transition state of an input/output terminal for each of the circuit components based on the circuit component transistor connection information information, by generating signal terminal transition information with a logic simulation performed for each of the circuit components of the integrated circuit, and by obtaining power consumption in a signal transition of an input/output terminal of ea
    Type: Application
    Filed: June 11, 2012
    Publication date: October 4, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Itsumi SUGIYAMA, Tomohiro TANAKA
  • Publication number: 20100079212
    Abstract: A semiconductor circuit apparatus having a clock oscillating circuit includes a first inverter circuit having a power supply terminal connected to a power supply potential via a first power supply potential connection transistor and a ground terminal connected to a ground potential via a first ground potential connection transistor, an inverter circuit block having a second inverter circuit connected to the power supply potential via a second power supply potential connection transistor and to the ground potential via a second ground potential connection transistor and connected to the first inverter circuit in parallel and a selection circuit block that outputs a power supply potential connection signal to any one of gate terminals of the first and second power supply potential connection transistors and a ground potential connection signal to any one of gate terminals of the first and second ground potential connection transistors.
    Type: Application
    Filed: September 18, 2009
    Publication date: April 1, 2010
    Applicant: Fujitsu Limited
    Inventor: Itsumi SUGIYAMA