Abstract: A semiconductor integrated circuit includes: a first circuit having a plurality of scan chains; a second circuit connected with input/output signals of the first circuit; and a third circuit connected with the second circuit through the first circuit. The plurality of scan chains comprises a first scan chain that contains flip-flops whose input/output signals are connected with the second circuit, and a second scan chain that does not contain any flip-flop whose input/output signal is connected with the second circuit. The flip-flops operate as a shift register at a scan path test, and when the third circuit exchanges signals with the second circuit through the flip-flops of the first scan chain, the second scan chain of the first circuit operates as a shift register.

Abstract: A semiconductor integrated circuit having an internal circuit which is tested based on a scanning method is provided. The internal circuit has: memory elements including a first memory element and a second memory element; combinational circuits including a first combinational circuit receiving an external input data, a second combinational circuit outputting an external output data and a third combinational circuit; a first selection circuit; and a second selection circuit. The first selection circuit receives the external input data and a stored data held by the first memory element, and outputs any of them to the first combinational circuit. The second selection circuit receives the external output data output from the second combinational circuit and an operation result data output from the third combinational circuit, and outputs any of them to the second memory element.

Abstract: A semiconductor integrated circuit includes: a first circuit having a plurality of scan chains; a second circuit connected with input/output signals of the first circuit; and a third circuit connected with the second circuit through the first circuit. The plurality of scan chains comprises a first scan chain that contains flip-flops whose input/output signals are connected with the second circuit, and a second scan chain that does not contain any flip-flop whose input/output signal is connected with the second circuit. The flip-flops operate as a shift register at a scan path test, and when the third circuit exchanges signals with the second circuit through the flip-flops of the first scan chain, the second scan chain of the first circuit operates as a shift register.

Abstract: A semiconductor integrated circuit having an internal circuit which is tested based on a scanning method is provided. The internal circuit has: memory elements including a first memory element and a second memory element; combinational circuits including a first combinational circuit receiving an external input data, a second combinational circuit outputting an external output data and a third combinational circuit; a first selection circuit; and a second selection circuit. The first selection circuit receives the external input data and a stored data held by the first memory element, and outputs any of them to the first combinational circuit. The second selection circuit receives the external output data output from the second combinational circuit and an operation result data output from the third combinational circuit, and outputs any of them to the second memory element.

Abstract: A multiplexer cell layout structure is a layout structure of primitive cells where cell arrays composed of P-channel transistors and N-channel transistors are arranged in two upper and lower rows. And, a plurality of transistors of transfer gates are arranged on the upper side and lower side of the cell arrays, an output terminal of the plurality of arranged transistors is connected up and down by Metal wiring across between the upper and lower cell arrays. Thus, a multiplexer cell layout structure which increases wiring tracks of two-layer metal wiring for a one-chip layout held by a 4-input multiplexer inverter can be obtained.

Abstract: A multiplexer cell layout structure is a layout structure of primitive cells where cell arrays composed of P-channel transistors and N-channel transistors are arranged in two upper and lower rows. And, a plurality of transistors of transfer gates are arranged on the upper side and lower side of the cell arrays, an output terminal of the plurality of arranged transistors is connected up and down by Metal wiring across between the upper and lower cell arrays. Thus, a multiplexer cell layout structure which increases wiring tracks of two-layer metal wiring for a one-chip layout held by a 4-input multiplexer inverter can be obtained.

Abstract: In a wiring designing method for a semiconductor integrated circuit, a signal line (201) is wired. Adjacent signal lines (204, 205), in which output ends (204o, 205o) are opened, are mounted adjacently to the signal line (201). A capacitance is calculated which are formed by the signal line (201) and the adjacent lines (204, 205). Line lengths (L2, L3) of the adjacent lines (204, 205) are adjusted in accordance with the capacitance. The capacitance is changed by the adjustment of the line lengths (L2, L3). Accordingly, it is possible to adjust the capacitance formed by the two signal lines adjacent to each other and a delay amount of the signal flowing through the signal line.

Abstract: Two adjacent lines are formed in parallel to a signal line in a wiring layer where the signal line is formed. Intersection lines are formed respectively in wiring layers above and under the wiring layers where the signal line and the adjacent lines are formed, along areas which are enclosed by the adjacent lines. Entire-line-area through-holes for connecting each of the adjacent lines with a corresponding one of the intersection line are formed along the entire area of the adjacent lines, in an insulating layer between the adjacent lines and the intersection lines. The signal line is completely covered by the adjacent lines, the intersection lines and the entire-line-area through-holes. The adjacent lines, the intersection lines and the entire-line-area through-holes are maintained at a constant potential, or their electric potentials have the same phase as that of the signal line.