Patents by Inventor Itsuo Sasaki
Itsuo Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6459416Abstract: A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit 311 for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit 321 for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit 341 for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit 311 or the second gray-level pattern generating circuit 321 when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.Type: GrantFiled: March 10, 1999Date of Patent: October 1, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Itsuo Sasaki, Yasoji Suzuki, Hirofumi Kato, Isao Arita, Toshio Yanagisawa, Kazuyoshi Yamamoto, Hiroyoshi Murata, Hiroyuki Hamagawa
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Patent number: 6020869Abstract: A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit 311 for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit 321 for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit 341 for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit 311 or the second gray-level pattern generating circuit 321 when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.Type: GrantFiled: April 30, 1997Date of Patent: February 1, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Itsuo Sasaki, Yasoji Suzuki, Hirofumi Kato, Isao Arita, Toshio Yanagisawa, Kazuyoshi Yamamoto, Hiroyoshi Murata, Hiroyuki Hamagawa
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Patent number: 4716308Abstract: A MOS logic circuit comprises two P channel MOSFETs connected in parallel between a positive power source V.sub.DD and a logic signal output terminal and two series circuits connected in parallel between a ground voltage source V.sub.SS and the terminal, each series circuit being comprised of serially connected two N channel MOSFETs. The gate electrodes of the MOSFETs located in the corresponding positions in the respective series circuits are connected to first and second logic signal input terminals, respectively. Similarly, the gate electrodes of the other MOSFETs located in the corresponding positions in the respective series circuits are connected to the second and first logic signal input terminals, respectively.Type: GrantFiled: July 29, 1983Date of Patent: December 29, 1987Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Kenji Matsuo, Itsuo Sasaki, Hiroaki Suzuki, Mitsuyuki Kunieda
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Patent number: 4592021Abstract: A data readout circuit for an MOS transistor array includes a plurality of data output lines. To each of the data output lines are connected N-channel MOS transistors of a corresponding row group. Each of P-channel data output line selection MOS transistors is connected between each of the data output lines and a data output node. An access time is shortened by controlling the data output line selection MOS transistors to be conductive while the data output lines and the data output node are both in a precharged state.Type: GrantFiled: July 29, 1983Date of Patent: May 27, 1986Assignee: Shibaura Kenki Kabushiki KaishaInventors: Hiroaki Suzuki, Itsuo Sasaki
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Patent number: 4558292Abstract: A low pass filter which comprises first, second and third switched capacitor circuits connected to a power source V.sub.DD and/or a power source V.sub.SS, first and second operational amplifiers driven by the power sources V.sub.DD and V.sub.SS, and a bias circuit connected between the power sources V.sub.DD and V.sub.SS for providing a bias voltage to the non-inverting input terminals of the first and second amplifiers.Type: GrantFiled: July 2, 1982Date of Patent: December 10, 1985Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Itsuo Sasaki, Kenji Matsuo
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Patent number: 4550295Abstract: A switched capacitor integrator is comprised of an operational amplifier, a feedback capacitor connected between the inverting input terminal and the output terminal of the amplifier, a bias circuit for applying a given voltage to the non-inverting input terminal of the amplifier, a switched capacitor, and a switch circuit which connects the switched capacitor between the signal input terminal applied with an input voltage signal and the inverting input terminal of the amplifier in a first operation mode and short-circuits the switched capacitor in a second operation mode.Type: GrantFiled: September 5, 1984Date of Patent: October 29, 1985Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventor: Itsuo Sasaki
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Patent number: 4546327Abstract: A signal corresponding to an analog input signal is supplied to one of two input terminals of a two-input, one-output MOS differential amplifier. A reference voltage signal is supplied to the other of the two input terminals of the MOS differential amplifier. A bipolar transistor having one end connected to an analog signal output terminal is driven by a signal from the output terminal of the MOS differential amplifier. A loudspeaker is driven by the bipolar transistor.Type: GrantFiled: July 13, 1983Date of Patent: October 8, 1985Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Yasoji Suzuki, Itsuo Sasaki, Shouji Abou
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Patent number: 4532494Abstract: A delta value generating circuit in an adaptive delta codec, comprising a delta value register, a control terminal for indicating increase or decrease of the delta value and adder/subtractor for increasing or decreasing the delta value in the register in accordance with a level at the control terminal. The adder/subtractor has first input terminals connected to the output terminals of the register and second input terminals connected to a predetermined number of upper bits of the output terminals of the register and the control terminal in accordance with a level at the control terminal.Type: GrantFiled: December 30, 1981Date of Patent: July 30, 1985Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Itsuo Sasaki, Hiroaki Suzuki, Masakazu Kamichika
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Patent number: 4524328Abstract: A MOS power amplifier circuit comprised of a load driver including two p-channel MOSFETs connected in series, a preamplifier for amplifying an analog input signal and supplying the amplified one to the gate of one of the MOSFETs and for rendering the impedance of the two MOSFETs low; and an inverting amplifier for invert-amplifying the output signal from the preamplifier and supplying the amplified one to the gate of the other MOSFET. The operating voltage of the preamplifier and the inverting amplifier is higher than that of the load driver.Type: GrantFiled: August 19, 1983Date of Patent: June 18, 1985Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Shouji Abou, Itsuo Sasaki
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Patent number: 4520283Abstract: A switched capacitor circuit has: first and second power sources; an operational amplifier driven by the power sources; a feedback capacitor connected to the inverting input terminal and the output terminal of the amplifier; a switched capacitor connected between a signal input terminal which receives an input signal voltage and the inverting input terminal of the amplifier; switching circuits for controlling the charging and discharging operations of the switched capacitor; and a bias circuit which is connected between the power sources and which applies a predetermined voltage to the non-inverting input terminal of the amplifier.Type: GrantFiled: July 2, 1982Date of Patent: May 28, 1985Inventors: Itsuo Sasaki, Hiroaki Suzuki
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Patent number: 4441169Abstract: A MOSFET random access memory having a memory cell, an independent write-in switching means and an independent read-out control circuit. The read-out control circuit includes a first MOS transistor controlled by the data stored in the memory cell and a second MOS transistor controlled by a read-out control signal. When the data stored in the memory cell is read out, charge flow between the memory cell and the data line is prevented which results in high reliability.Type: GrantFiled: February 23, 1982Date of Patent: April 3, 1984Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Itsuo Sasaki, Hiroaki Suzuki