Patents by Inventor Itzic Cohen

Itzic Cohen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12625624
    Abstract: Systems, methods, and devices provide management of power domains. Methods include activating a first power domain of a memory controller in response to receiving a memory command associated with a storage location coupled to the memory controller, and performing a first portion of a sequence of operations determined based on the memory command, the first portion being performed using a first plurality of processing elements included in the first power domain. Methods further include activating a second power domain of the memory controller based on a timing determined by the sequence of operations, and performing a second portion of the sequence of operations using a second plurality of processing elements included in the second power domain.
    Type: Grant
    Filed: December 14, 2023
    Date of Patent: May 12, 2026
    Assignee: Infineon Technologies LLC
    Inventors: Itzic Cohen, Yair Sofer, Guy Levi, Eran Geyari
  • Publication number: 20260127109
    Abstract: Systems, methods, and devices prevent data loss in memory devices. Systems may include a non-volatile memory device that includes a first data unit configured to store data for the non-volatile memory device and associated metadata, and a second data unit configured to store data for the non-volatile memory device and associated metadata, wherein the first data unit and second data unit are configured to alternate storing a most recent version of the data and associated metadata. The systems may also include control circuitry configured to read metadata from the first data unit and the second data unit, identify the first data unit as an inactive data unit based on contents of the first data unit and the second data unit, and perform one or more update operations such that the first data unit is updated and set as an active unit when the update operations are complete.
    Type: Application
    Filed: November 3, 2025
    Publication date: May 7, 2026
    Applicant: Infineon Technologies LLC
    Inventors: Amichai GIVANT, Yoav YOGEV, Shivananda SHETTY, Stefano AMATO, Itzic COHEN, Idan KOREN, Yair SOFER
  • Patent number: 12481578
    Abstract: Systems, methods, and devices prevent data loss in memory devices. Systems may include a non-volatile memory device that includes a first data unit configured to store data for the non-volatile memory device and associated metadata, and a second data unit configured to store data for the non-volatile memory device and associated metadata, wherein the first data unit and second data unit are configured to alternate storing a most recent version of the data and associated metadata. The systems may also include control circuitry configured to read metadata from the first data unit and the second data unit, identify the first data unit as an inactive data unit based on contents of the first data unit and the second data unit, and perform one or more update operations such that the first data unit is updated and set as an active unit when the update operations are complete.
    Type: Grant
    Filed: October 12, 2023
    Date of Patent: November 25, 2025
    Assignee: Infineon Technologies LLC
    Inventors: Amichai Givant, Yoav Yogev, Shivananda Shetty, Stefano Amato, Itzic Cohen, Idan Koren, Yair Sofer
  • Publication number: 20250199697
    Abstract: Systems, methods, and devices provide management of power domains. Methods include activating a first power domain of a memory controller in response to receiving a memory command associated with a storage location coupled to the memory controller, and performing a first portion of a sequence of operations determined based on the memory command, the first portion being performed using a first plurality of processing elements included in the first power domain. Methods further include activating a second power domain of the memory controller based on a timing determined by the sequence of operations, and performing a second portion of the sequence of operations using a second plurality of processing elements included in the second power domain.
    Type: Application
    Filed: December 14, 2023
    Publication date: June 19, 2025
    Applicant: Infineon Technologies LLC
    Inventors: Itzic Cohen, Yair Sofer, Guy Levi, Eran Geyari
  • Publication number: 20240296115
    Abstract: Systems, methods, and devices prevent data loss in memory devices. Systems may include a non-volatile memory device that includes a first data unit configured to store data for the non-volatile memory device and associated metadata, and a second data unit configured to store data for the non-volatile memory device and associated metadata, wherein the first data unit and second data unit are configured to alternate storing a most recent version of the data and associated metadata. The systems may also include control circuitry configured to read metadata from the first data unit and the second data unit, identify the first data unit as an inactive data unit based on contents of the first data unit and the second data unit, and perform one or more update operations such that the first data unit is updated and set as an active unit when the update operations are complete.
    Type: Application
    Filed: October 12, 2023
    Publication date: September 5, 2024
    Applicant: Infineon Technologies LLC
    Inventors: Amichai GIVANT, Yoav YOGEV, Shivananda SHETTY, Stefano AMATO, Itzic COHEN, Idan KOREN, Yair SOFER
  • Patent number: 7945825
    Abstract: Disclosed are methods and circuits for performing recovery associated with programming of non-volatile memory (NVM) array cells. According to embodiments, there are provided methods and circuits for programming NVM cells, including: (1) erasing NVM array cells; (2) loading an SRAM with user data; (3) if programming is successful, then flipping bits in the SRAM; and (4) if programming is not successful, reading data back from the array to the SRAM.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: May 17, 2011
    Assignee: Spansion Isreal, Ltd
    Inventors: Itzic Cohen, Ori Tirosh, Kobi Danon, Shmulik Hadas
  • Publication number: 20090228739
    Abstract: A method of performing recovery in conjunction with programming an array of NVM cells. First, erasing the array cells and loading an SRAM with user data. When programming the cells, flip bits in the SRAM which are successfully programmed (pass PV). If programming is not successful, read the failed data from the array, and if the SRAM bits were not successfully programmed, do not change them. Write the other bits (not programmed or successfully programmed) from the array to the SRAM. Before reading the failed data, the SRAM may be copied to a second SRAM. If the restore did not work, an ED mechanism may be applied, and if the ED bits to not align with the data, move a read reference (RD), copy the second SRAM to the original SRAM, and attempt reading again, until the data is successfully recovered.
    Type: Application
    Filed: November 25, 2008
    Publication date: September 10, 2009
    Inventors: Itzic Cohen, Ori Tirosh, Kobi Danon, Shmulik Hadas