Abstract: An a.c. coupled multistage high gain operational amplifier includes at least two gain stages, each having an input and an output; an a.c. coupling level shifting capacitance interconnecting the output of a first stage to the input of a second stage; and a charging circuit interconnecting with the a.c. coupling level shifting capacitance and the input of the second stage to charge the a.c. coupling level shifting capacitance in a track phase and to connect the a.c. coupling capacitance to the input of the second stage during a hold phase for dissociating the bias voltages of the stages.

Abstract: A differential variable gain amplifier (VGA) with constant input impedance and an adjustable one-pole filtering characteristic is provided. Each input of the VGA has a set of parallel resistors connected thereto. Except for one resistor in each set, each of the resistors of the two sets is connected to its corresponding summing junction (op-amp input), or to a corresponding resistor of the other set via a switch. Switching the resistors to their corresponding summing junction or to the corresponding resistor of the other set provides for the variable gain function, where the gain is proportional to the number of resistors connected to the summing junction. The configuration of resistors provides a constant input impedance to the VGA of R/(n+1), where R is the resistance value of the resistors.

Abstract: A tunable, active RC filter and method of tuning the active RC filter which prevents distortions introduced during tuning. Generally, each tuning element in the feedback loop of the tunable active RC filter comprises a capacitor, a first switch, a second switch, and a third switch. The first switch connects a first terminal of the capacitor to a summing junction at the input of the op-amp when closed. When closed, a second switch connects the first terminal of the capacitor to a replica of the voltage present at the summing junction (input) of the op-amp to which the first terminal of the reactance element is connectable via the first switch. A third switch, when closed, connects the first terminal of the capacitor to the second terminal of the reactance element, which is connected the output of the op-amp.

Abstract: An analog-to-digital converter including a quantizer and a residue generator, both of which sample an input voltage in parallel. The sampling characteristics of each of the residue generator and the quantizer are designed to substantially match one another. This converter may be used as a low-power ADC front-end circuit that does not require a dedicated sampleand-hold circuit. The front-end circuit consists of two substantially-matched sampling networks, one for the residue generator and the other for the quantizer, inside the first stage of the converter.

Abstract: An analog-to-digital converter including a quantizer and a residue generator, both of which sample an input voltage in parallel. The sampling characteristics of each of the residue generator and the quantizer are designed to substantially match one another. This converter may be used as a low-power ADC front-end circuit that does not require a dedicated sample-and-hold circuit. The front-end circuit consists of two substantially-matched sampling networks, one for the residue generator and the other for the quantizer, inside the first stage of the converter.

Abstract: A method and system for high bandwidth, high gain offset compensation in a read channel integrated circuit includes zeroing the analog read signal applied to the signal path at a first location in the read channel integrated circuit path prior to a first amplifier which has a first gain and a first bandwidth magnitude characteristic with a high frequency boost; coupling a signal from the first amplifier to a second amplifier which has a second gain larger than the first and a second bandwidth magnitude characteristic having high frequency roll-off; and further coupling the signal further from the second amplifier to a storage device and feeding back the signal stored in the storage device to the first amplifier to apply the high frequency boost of the first bandwidth magnitude characteristic to compensate for the high frequency roll-off of the second bandwidth magnitude characteristic; decoupling the signal from the storage device and removing the zeroing of the analog read signal applied to the signal path.

Abstract: This invention provides apparatus and a method to assist in calibrating a read channel in a magnetic data storage system. More particularly, the invention provides a read channel including a digital noise generator. During a calibration procedure, the digital noise generator injects an analog noise signal into the read channel, thereby increasing the read channel's bit-error rate, and consequently allowing rapid calibration of the read channel. The digital noise generator comprises a number of linear feedback shift registers that together generate a pseudo-random digital word sequence, and a digital-to-analog converter that converts the pseudo-random digital word sequence into the analog noise signal. The digital-to-analog converter comprises a plurality of one-bit digital-to-analog converters whose outputs are summed by an analog adder.