Abstract: Disclosed is an electrostatic discharge (ESD) protection structure for a circuit component connected to a first pad by an interconnect. The structure includes: a trigger circuit; a trigger circuit disconnect switch connected between the interconnect and trigger circuit; and a discharge circuit connected to a trigger voltage output node of the trigger circuit and to the interconnect. The switch enables the interconnect to be disconnected from the trigger circuit during testing of the circuit component (e.g., during wafer level testing to assess gate integrity) and to otherwise be continuously connected to the trigger circuit to facilitate ESD protection. The switch can be a depletion mode high electron mobility transistor (HEMT) with a gate connected to a second pad, which is connected to receive a negative voltage during testing and which is otherwise left floating. Also disclosed are a package chip including the ESD protection structure and associated methods.