Abstract: Data that is initially stored in Single Level Cell (SLC) blocks is subsequently copied (folded) to a Multi Level Cell (MLC) block where the data is stored in MLC format, the data copied in a minimum unit of a fold-set, the MLC block including a plurality of separately-selectable sets of NAND strings, data of an individual fold-set copied exclusively to two or more word lines of an individual separately-selectable set of NAND strings in the MLC block.

Abstract: When the number of bad columns in a memory or plane is less than a threshold number then a first Error Correction Code (ECC) scheme encodes user data in first pages of a first size. If the number of bad columns is greater than the threshold number then a second ECC scheme encodes the user data in second pages of a second size that is smaller than the first size.

Abstract: Partially-bad blocks are identified in a 3-D block-erasable nonvolatile memory, each partially-bad block having one or more inoperable separately-selectable sets of NAND strings and one or more operable separately-selectable sets of NAND strings. Operable sets of NAND strings within two or more partially-bad blocks are identified and are mapped to form one or more virtual blocks that are individually assigned virtual block addresses. The virtual block address are maintained in a list and used to access the virtual blocks.

Abstract: Non-volatile memory systems with multi-write direction memory units are disclosed. In one implementation an apparatus comprises a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to select an empty memory block of the non-volatile memory for the storage of data; examine an identifier associated with the memory block to determine a write direction for the storage of data; and write data to the memory block beginning with an initial word line of the memory block or a last word line of the memory block dependent on the write direction. The controller is further configured to erase the memory unit and, in response to erasing the memory unit, modify the identifier to change the write direction for a subsequent write of data to the memory block.

Abstract: Non-volatile memory systems with multi-write direction memory units are disclosed. In one implementation an apparatus comprises a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to select an empty memory block of the non-volatile memory for the storage of data; examine an identifier associated with the memory block to determine a write direction for the storage of data; and write data to the memory block beginning with an initial word line of the memory block or a last word line of the memory block dependent on the write direction. The controller is further configured to erase the memory unit and, in response to erasing the memory unit, modify the identifier to change the write direction for a subsequent write of data to the memory block.

Abstract: When the number of bad columns in a memory or plane is less than a threshold number then a first Error Correction Code (ECC) scheme encodes user data in first pages of a first size. If the number of bad columns is greater than the threshold number then a second ECC scheme encodes the user data in second pages of a second size that is smaller than the first size.

Abstract: Data that is initially stored in Single Level Cell (SLC) blocks is subsequently copied (folded) to a Multi Level Cell (MLC) block where the data is stored in MLC format, the data copied in a minimum unit of a fold-set, the MLC block including a plurality of separately-selectable sets of NAND strings, data of an individual fold-set copied exclusively to two or more word lines of an individual separately-selectable set of NAND strings in the MLC block.

Abstract: Partially-bad blocks are identified in a 3-D block-erasable nonvolatile memory, each partially-bad block having one or more inoperable separately-selectable sets of NAND strings and one or more operable separately-selectable sets of NAND strings. Operable sets of NAND strings within two or more partially-bad blocks are identified and are mapped to form one or more virtual blocks that are individually assigned virtual block addresses. The virtual block address are maintained in a list and used to access the virtual blocks.