Abstract: A regulator clamp circuit includes a comparison circuit having a sample and hold circuit. The comparison circuit compares a regulated voltage with a sampled voltage of the regulated voltage from a previous time. In some embodiments, the sampled voltage can be determined during a sampling phase that occurs prior to a clamp regulation phase. During the clamp regulation phase, the comparison circuit compares the regulated voltage with the sampled voltage and outputs a signal to activate an actuator circuit to clamp the regulated voltage when the regulated voltage terminal has a higher amount of charge than desired.

Abstract: An analog switch circuit is provided. The circuit includes a branch coupled between an input terminal and an output terminal. The branch is configured to transfer an input signal at the input terminal to the output terminal when a control signal is at a first state. A transistor in the branch includes a current electrode coupled at the input terminal and is configured for receiving the input signal having a voltage exceeding a voltage rating of the transistor. A level shifter includes an output coupled to a control electrode of the transistor and is configured to provide a first voltage sufficient to cause the transistor to be conductive without exceeding the voltage rating of the first transistor when the control signal is at the first state. A voltage generator is coupled to the level shifter and is configured to generate the first voltage based on the input signal.

Abstract: A low voltage level shifter that is suitable for use with subthreshold logic. In one embodiment, the low voltage level shifter includes first and second input transistors coupled to first and second input nodes, respectively, that receive complementary low voltage input signals. A circuit is coupled to the first and second input transistors and to first and second output nodes that generate complementary high voltage output signals. The circuit is configured to transmit a first current to the second output node when the first input transistor is activated, wherein the first current is substantially equal to current drawn by the first input transistor when it is activated. The circuit is also configured to transmit a second current to the first output node when the second input transistor is activated, wherein the second current is substantially equal to current drawn by the second input transistor when it is activated.

Abstract: A low voltage level shifter that is suitable for use with subthreshold logic. In one embodiment, the low voltage level shifter includes first and second input transistors coupled to first and second input nodes, respectively, that receive complementary low voltage input signals. A circuit is coupled to the first and second input transistors and to first and second output nodes that generate complementary high voltage output signals. The circuit is configured to transmit a first current to the second output node when the first input transistor is activated, wherein the first current is substantially equal to current drawn by the first input transistor when it is activated. The circuit is also configured to transmit a second current to the first output node when the second input transistor is activated, wherein the second current is substantially equal to current drawn by the second input transistor when it is activated.

Abstract: An integrated circuit includes a digital logic circuit, a multiplexer (MUX) having a first and a second data input, a control input, and an output coupled to an input of the digital logic circuit. The second data input is coupled to receive a high frequency clock signal. The integrated circuit includes a very low frequency (VLF) clock is configured to provide a VLF clock signal when enabled, and a counter coupled to receive the VLF clock signal and configured to toggle an output of the counter upon counting a predetermined number of cycles of the VLF clock signal. The output of the counter is coupled to the first data input of the MUX. The MUX is configured to provide the first data input as the output of the MUX during a low power mode, and otherwise to provide the second data input as the output of the MUX.

Abstract: A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.

Abstract: A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.

Abstract: An integrated circuit includes a digital logic circuit having a first transistor and a second transistor, a replica circuit having a first transistor and a second transistor which replicate the first transistor and second transistor of the digital logic circuit, and a storage circuit configured to store a static state indicator. The circuit also includes a comparison circuit configured to compare threshold voltages of the first and second transistor of the replica circuit, and having an output coupled to provide the static state indicator to the storage circuit, and a selection circuit configured to provide the state indicator to an input of the digital logic circuit and an input of the replica circuit during a lower power mode and to provide a run mode signal instead of the state indicator to the input of the digital logic signal and the input of the replica circuit during a high power mode.

Abstract: An Integrated Circuit (IC) as described herein may include a first logic circuit, a second logic circuit coupled to the first logic circuit via a level shifter, and a safe state circuit coupled to the first logic circuit and to a first input of a logic gate. For example, a second input of the logic gate may be coupled to an output of the level shifter, and an output of the logic gate may be coupled to the second logic circuit. The safe state circuit may further include a front-end portion; a reversible current mirror portion coupled to the front-end portion; and a voltage-level translation portion coupled to the reversible current mirror portion.

Abstract: A circuit includes first, second, and third power supply terminals. The circuit includes an input node coupled to receive a negative voltage and an output node coupled to provide a positive voltage proportional to the negative voltage. The circuit includes a voltage-to-current converter coupled to the first power supply terminal and the input node and configured to generate an intermediate current proportional to the negative voltage at the input node. The circuit also includes a current mirror coupled to the second power supply terminal and third power supply terminal and configured to mirror the intermediate current through a first resistor to provide the positive proportional voltage.

Abstract: A sample and hold circuit including a charge path coupled to a voltage source. A first node of the charge path is located closer to the voltage source in the charge path than a second node of the charge path. The second node is coupled to an output of the sample and hold circuit to provide an output voltage. The sample and hold circuit includes a comparator circuit that compares the voltage of the first node and the voltage of the second node. When the comparator circuit determines that the voltage of the first node is a first condition with respect to a voltage of the second node, a voltage source provides a charging voltage on the first path to charge a first capacitor and a second capacitor to the charging voltage.

Abstract: A sample and hold circuit including a charge path coupled to a voltage source. A first node of the charge path is located closer to the voltage source in the charge path than a second node of the charge path. The second node is coupled to an output of the sample and hold circuit to provide an output voltage. The sample and hold circuit includes a comparator circuit that compares the voltage of the first node and the voltage of the second node. When the comparator circuit determines that the voltage of the first node is a first condition with respect to a voltage of the second node, a voltage source provides a charging voltage on the first path to charge a first capacitor and a second capacitor to the charging voltage.

Abstract: Embodiments of a charge pump circuit and a method for operating a charge pump circuit are disclosed. In an embodiment, a charge pump circuit includes a charge pump configured to generate a charge pump output voltage, a transistor array including multiple transistor devices that includes at least one transistor device having a back gate terminal coupled to the charge pump output voltage, and a control circuit configured to control the charge pump output voltage so as to regulate the back bias voltage of the transistor devices within the transistor array. Other embodiments are also described.

Abstract: Embodiments of a charge pump circuit and a method for operating a charge pump circuit are disclosed. In an embodiment, a charge pump circuit includes a charge pump configured to generate a charge pump output voltage, a transistor array including multiple transistor devices that includes at least one transistor device having a back gate terminal coupled to the charge pump output voltage, and a control circuit configured to control the charge pump output voltage so as to regulate the back bias voltage of the transistor devices within the transistor array. Other embodiments are also described.

Abstract: A device includes a current source circuit to separately provide a first current and a second current and a thermal detection device coupleable to the output of the current source circuit. The device further includes a voltage detection circuit to provide a first indicator of a first voltage representative of a voltage at the thermal detection device in response to the second current and a second indicator of a second voltage representative of a voltage difference between the voltage at the thermal detection device in response to the second current and a voltage at the voltage detection device in response to the first current. The device further includes a temperature detection circuit to provide an over-temperature indicator based on the first indicator and the second indicator, wherein an operation of a circuit component of the device can be adjusted based on the over-temperature indicator.

Abstract: A method and apparatus are described for providing a current mirror type high voltage switching circuit (60) having a reference branch (M2, M3, R1) and a tracking branch (M1, M5), where the output peak current is limited by adding an additional branch (M4, M6) to the current mirror circuit which includes an additional mirror transistor (M4) and cascode transistor (M6), and where over voltage protection is provided by including a shut-off circuit (Q1, Q2) which turns “OFF” the cascode transistors (M5-M8) whenever the output voltage (Vout) exceeds the first reference voltage (Vbat) by a predetermined amount.

Abstract: Systems and methods are provided for determining the value of a capacitance. A system for sensing capacitance comprises an oscillator arrangement comprising a plurality of oscillators and a mismatch compensation arrangement coupled between the oscillator arrangement and a first capacitive element having a first capacitance. The mismatch compensation arrangement is configured to selectively couple the first capacitive element to a respective oscillator of the plurality of oscillators, wherein an oscillation frequency of the respective oscillator is influenced by the first capacitance.

Abstract: A device includes a current source circuit to separately provide a first current and a second current and a thermal detection device coupleable to the output of the current source circuit. The device further includes a voltage detection circuit to provide a first indicator of a first voltage representative of a voltage at the thermal detection device in response to the second current and a second indicator of a second voltage representative of a voltage difference between the voltage at the thermal detection device in response to the second current and a voltage at the voltage detection device in response to the first current. The device further includes a temperature detection circuit to provide an over-temperature indicator based on the first indicator and the second indicator, wherein an operation of a circuit component of the device can be adjusted based on the over-temperature indicator.

Abstract: Systems and methods are provided for determining the value of a capacitance. A system for sensing capacitance comprises an oscillator arrangement comprising a plurality of oscillators and a mismatch compensation arrangement coupled between the oscillator arrangement and a first capacitive element having a first capacitance. The mismatch compensation arrangement is configured to selectively couple the first capacitive element to a respective oscillator of the plurality of oscillators, wherein an oscillation frequency of the respective oscillator is influenced by the first capacitance.

Abstract: A method and apparatus are described for providing a current mirror type high voltage switching circuit (60) having a reference branch (M2, M3, R1) and a tracking branch (M1, M5), where the output peak current is limited by adding an additional branch (M4, M6) to the current mirror circuit which includes an additional mirror transistor (M4) and cascode transistor (M6), and where over voltage protection is provided by including a shut-off circuit (Q1, Q2) which turns “OFF” the cascode transistors (M5-M8) whenever the output voltage (Vout) exceeds the first reference voltage (Vbat) by a predetermined amount.