Patents by Inventor Ivan Carlos Ribeiro Nascimento
Ivan Carlos Ribeiro Nascimento has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9644593Abstract: Systems and methods for managing cold-crank events. In an embodiment, a method may include detecting a cold-crank event and setting a switching circuit to a non-conductive state, where the switching circuit is configured to couple a first regulator to a memory circuit such that setting the switching circuit to the non-conductive state de-couples the memory circuit from the first regulator. The method may also include setting the switching circuit to a conductive state in current limitation mode during a recovery period following the cold-crank event to re-couple the memory circuit to the first regulator. In another embodiment, an electronic device include a switching circuit, a first regulator coupled to a first terminal of the switching circuit, a second regulator coupled to a second terminal of the switching circuit, a logic circuit coupled to the switching circuit, and a memory circuit coupled to the second terminal of the switching circuit.Type: GrantFiled: January 29, 2014Date of Patent: May 9, 2017Assignee: NXP USA, INC.Inventors: Adriano Marques Pereira, Sunny Gupta, Andre Luis Vilas Boas, Pedro Barbosa Zanetta, Ivan Carlos Ribeiro Nascimento, Carl Culshaw
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Patent number: 9509305Abstract: In an embodiment, an electronic device includes an integrated circuit (IC) having a plurality of power domains, a first regulator coupled to a given power domain, a second regulator coupled to the given power domain, and a switching circuit coupled between the first and second regulators and configured to control an amount of current drawn by the power domain from the first and/or second regulators. In another embodiment, a method includes controlling an impedance of a switching circuit to change an amount of current, the switching circuit coupled to a given power domain of an IC configured to operate in a first mode followed by a second mode, where the switching circuit is coupled to a first regulator configured to provide more power to the IC than a second regulator, and a transition period includes turning off the first regulator and turning on the second regulator.Type: GrantFiled: January 9, 2014Date of Patent: November 29, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Ivan Carlos Ribeiro Nascimento, Akshat Gupta, Sunny Gupta, Akshay K. Pathak, Adriano Marques Pereira, Garima Sharda, Pedro Barbosa Zanetta
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Patent number: 9459636Abstract: Systems and methods for transition control in a hybrid Switched-Mode Power Supply (SMPS). In some embodiments, a hybrid SMPS may include linear circuitry configured to produce an output voltage proportional to a variable duty cycle when the SMPS operates in linear mode and hysteretic circuitry coupled to the linear circuitry, the hysteretic circuitry configured to cause the duty cycle to assume one of two predetermined values when the SMPS operates in hysteretic mode. The hybrid SMPS may also include transition circuitry coupled to the linear circuitry and to the hysteretic circuitry, the transition circuitry configured to bypass at least a portion of the linear circuitry in response to the hybrid SMPS transitioning from the hysteretic mode to the linear mode.Type: GrantFiled: February 22, 2013Date of Patent: October 4, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Ivan Carlos Ribeiro Nascimento, Edevaldo Pereira Silva, Jr.
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Patent number: 9143115Abstract: An integrated circuit includes a delay compensation circuit (221, 222) that further includes a terminal for receiving a varying signal from a circuit external to the integrated circuit; a sampler circuit that samples and holds a present value of the varying signal at each occurrence of a transition in a digital signal; an integrator, coupled to the sampler circuit, that integrates a voltage difference between a sample of the varying signal and a reference signal, and that outputs results of the integration, wherein a time constant of the integrator is greater than a period of the varying signal; a waveform generator that generates a decreasing voltage in response to a transition in a second digital signal; and a comparator that has one input terminal for receiving the decreasing voltage, an inverted input terminal for receiving the results, and an output terminal for outputting a signal that generates an output signal.Type: GrantFiled: March 5, 2015Date of Patent: September 22, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Ivan Carlos Ribeiro Nascimento, Andre Luis Vilas Boas
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Patent number: 9110484Abstract: Temperature dependent biasing for leakage power reduction. In some embodiments, a semiconductor device may include a biasing circuit configured to generate a voltage that varies dependent upon a temperature of the semiconductor device and a logic circuit operably coupled to the biasing circuit, where the voltage is applied to a bulk terminal of one or more transistors within the logic circuit, and where the voltage has a value outside of a voltage supply range of the logic circuit. In another embodiment, a semiconductor device may include a biasing circuit configured to generate a voltage that varies according to a temperature of the semiconductor device and a power switch operably coupled to the biasing circuit, where the voltage is applied to a gate terminal of the power switch, and where the voltage has a value outside of a voltage supply range of the power switch.Type: GrantFiled: September 24, 2013Date of Patent: August 18, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Pedro Barbosa Zanetta, Ivan Carlos Ribeiro Nascimento
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Publication number: 20150211470Abstract: Systems and methods for managing cold-crank events. In an embodiment, a method may include detecting a cold-crank event and setting a switching circuit to a non-conductive state, where the switching circuit is configured to couple a first regulator to a memory circuit such that setting the switching circuit to the non-conductive state de-couples the memory circuit from the first regulator. The method may also include setting the switching circuit to a conductive state in current limitation mode during a recovery period following the cold-crank event to re-couple the memory circuit to the first regulator. In another embodiment, an electronic device include a switching circuit, a first regulator coupled to a first terminal of the switching circuit, a second regulator coupled to a second terminal of the switching circuit, a logic circuit coupled to the switching circuit, and a memory circuit coupled to the second terminal of the switching circuit.Type: ApplicationFiled: January 29, 2014Publication date: July 30, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Adriano Marques Pereira, Sunny Gupta, Andre Luis Vilas Boas, Pedro Barbosa Zanetta, Ivan Carlos Ribeiro Nascimento, Carl Culshaw
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Patent number: 9092043Abstract: Power switches with current limitation and zero Direct Current (DC) power consumption. In an embodiment, an integrated circuit includes switching circuitry coupled between a voltage supply node and a given one of a plurality of power domains, the switching circuitry configured to limit an amount of current drawn by the given power domain from the voltage supply node during a transition period, the switching circuitry further configured to consume zero DC power outside of the transition period. In another embodiment, a method includes controlling, via a switching circuit coupled between a voltage supply and an integrated circuit, an amount of current drawn by the integrated circuit from the voltage supply during a transition period; and causing the switching circuit to consume no static power during periods of time other than the transition period.Type: GrantFiled: August 22, 2013Date of Patent: July 28, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventor: Ivan Carlos Ribeiro Nascimento
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Patent number: 9092045Abstract: Startup circuits with native transistors. In some embodiments, a startup circuit may include a first inverter configured to receive a bandgap voltage (Vbg) from a bandgap reference circuit and to produce an output voltage (VOUT), and a second inverter operably coupled to the first inverter to form a latch, the latch configured to maintain a value of VOUT, the second inverter including a native transistor, the native transistor having a gate terminal coupled to VOUT and a source terminal coupled to Vbg. In other embodiments, a method may include receiving Vbg at a startup circuit and outputting VOUT configured to change in response to Vbg rising above Vtrig or falling below Vtrig, where the power consumption of the startup circuit is based at least in part upon a voltage value applied to a source terminal of a native transistor within the startup circuit.Type: GrantFiled: April 18, 2013Date of Patent: July 28, 2015Assignee: Freescale Semiconductor, Inc.Inventor: Ivan Carlos Ribeiro Nascimento
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Publication number: 20150194887Abstract: In an embodiment, an electronic device includes an integrated circuit (IC) having a plurality of power domains, a first regulator coupled to a given power domain, a second regulator coupled to the given power domain, and a switching circuit coupled between the first and second regulators and configured to control an amount of current drawn by the power domain from the first and/or second regulators. In another embodiment, a method includes controlling an impedance of a switching circuit to change an amount of current, the switching circuit coupled to a given power domain of an IC configured to operate in a first mode followed by a second mode, where the switching circuit is coupled to a first regulator configured to provide more power to the IC than a second regulator, and a transition period includes turning off the first regulator and turning on the second regulator.Type: ApplicationFiled: January 9, 2014Publication date: July 9, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Ivan Carlos Ribeiro Nascimento, Akshat Gupta, Sunny Gupta, Akshay K. Pathak, Adriano Marques Pereira, Garima Sharda, Pedro Barbosa Zanetta
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Publication number: 20150180454Abstract: An integrated circuit includes a delay compensation circuit (221, 222) that further includes a terminal for receiving a varying signal from a circuit external to the integrated circuit; a sampler circuit that samples and holds a present value of the varying signal at each occurrence of a transition in a digital signal; an integrator, coupled to the sampler circuit, that integrates a voltage difference between a sample of the varying signal and a reference signal, and that outputs results of the integration, wherein a time constant of the integrator is greater than a period of the varying signal; a waveform generator that generates a decreasing voltage in response to a transition in a second digital signal; and a comparator that has one input terminal for receiving the decreasing voltage, an inverted input terminal for receiving the results, and an output terminal for outputting a signal that generates an output signal.Type: ApplicationFiled: March 5, 2015Publication date: June 25, 2015Inventors: Ivan Carlos Ribeiro NASCIMENTO, Andre Luis VILAS BOAS
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Patent number: 9041366Abstract: A device (200) includes a circuit (202) and a driver stage (204) therefor. The circuit includes two sub-circuits (231 and 232). The driver stage includes switcher logic (206) that produces signals that control switching on and off of the sub-circuits. The switcher logic also produces other signals in advance of the signals that control the switching of the sub-circuits. The driver stage includes delay compensations circuits (221 and 222), coupled to the switcher logic and to the circuit, that produce timing signals for the switcher logic. The timing signals are closely aligned with moments that a changing voltage at a node between the sub-circuits passes through threshold voltages. The timing signals compensate for all delays of signals through the device such that a period that both sub-circuits are off is minimized, while ensuring that both sub-circuits are not on at a same time.Type: GrantFiled: April 27, 2012Date of Patent: May 26, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Ivan Carlos Ribeiro Nascimento, Andre Luis Vilas Boas
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Publication number: 20150084684Abstract: Temperature dependent biasing for leakage power reduction. In some embodiments, a semiconductor device may include a biasing circuit configured to generate a voltage that varies dependent upon a temperature of the semiconductor device and a logic circuit operably coupled to the biasing circuit, where the voltage is applied to a bulk terminal of one or more transistors within the logic circuit, and where the voltage has a value outside of a voltage supply range of the logic circuit. In another embodiment, a semiconductor device may include a biasing circuit configured to generate a voltage that varies according to a temperature of the semiconductor device and a power switch operably coupled to the biasing circuit, where the voltage is applied to a gate terminal of the power switch, and where the voltage has a value outside of a voltage supply range of the power switch.Type: ApplicationFiled: September 24, 2013Publication date: March 26, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Pedro Barbosa Zanetta, Ivan Carlos Ribeiro Nascimento
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Publication number: 20150054477Abstract: Power switches with current limitation and zero Direct Current (DC) power consumption. In an embodiment, an integrated circuit includes switching circuitry coupled between a voltage supply node and a given one of a plurality of power domains, the switching circuitry configured to limit an amount of current drawn by the given power domain from the voltage supply node during a transition period, the switching circuitry further configured to consume zero DC power outside of the transition period. In another embodiment, a method includes controlling, via a switching circuit coupled between a voltage supply and an integrated circuit, an amount of current drawn by the integrated circuit from the voltage supply during a transition period; and causing the switching circuit to consume no static power during periods of time other than the transition period.Type: ApplicationFiled: August 22, 2013Publication date: February 26, 2015Applicant: Freescale Semiconductor, Inc.Inventor: Ivan Carlos Ribeiro Nascimento
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Patent number: 8935117Abstract: A testing circuit in an integrated circuit indirectly measures a voltage at a node of other circuitry in the integrated circuit. The testing circuit includes a transistor having a control electrode, a first conducting electrode coupled to a first pad, a second conducting electrode coupled to a terminal of a power supply, and one or more switches for selectively coupling the control electrode to one of the node and a second pad. A method includes determining a relationship between drain current and gate voltage of the transistor when the control electrode is coupled to the second pad. A voltage at the node is determined by relating the current through the first conducting electrode of the transistor when control electrode is coupled to the node.Type: GrantFiled: March 9, 2012Date of Patent: January 13, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Walter Luis Tercariol, Richard T. L. Saez, Fernando Zampronho Neto, Ivan Carlos Ribeiro Nascimento
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Patent number: 8901991Abstract: Power monitoring circuitry. In some embodiments, comparator circuitry may be configured to receive a first voltage value and a second voltage value, and to identify the greater of the first and second voltage values. Selector circuitry coupled to the comparator circuitry may be configured to power one or more components within the comparator circuitry with a supply voltage corresponding to the greater voltage value. In other embodiments, a method may include identifying, via a comparator, the largest among a plurality of voltage values, and powering one or more logic components within the comparator with the identified voltage value.Type: GrantFiled: March 21, 2013Date of Patent: December 2, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Pedro Barbosa Zanetta, Ivan Carlos Ribeiro Nascimento
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Publication number: 20140312875Abstract: Startup circuits with native transistors. In some embodiments, a startup circuit may include a first inverter configured to receive a bandgap voltage (Vbg) from a bandgap reference circuit and to produce an output voltage (VOUT), and a second inverter operably coupled to the first inverter to form a latch, the latch configured to maintain a value of VOUT, the second inverter including a native transistor, the native transistor having a gate terminal coupled to VOUT and a source terminal coupled to Vbg. In other embodiments, a method may include receiving Vbg at a startup circuit and outputting VOUT configured to change in response to Vbg rising above Vtrig or falling below Vtrig, where the power consumption of the startup circuit is based at least in part upon a voltage value applied to a source terminal of a native transistor within the startup circuit.Type: ApplicationFiled: April 18, 2013Publication date: October 23, 2014Applicant: Freescale Semiconductor, Inc.Inventor: Ivan Carlos Ribeiro Nascimento
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Publication number: 20140285239Abstract: Power monitoring circuitry. In some embodiments, comparator circuitry may be configured to receive a first voltage value and a second voltage value, and to identify the greater of the first and second voltage values. Selector circuitry coupled to the comparator circuitry may be configured to power one or more components within the comparator circuitry with a supply voltage corresponding to the greater voltage value. In other embodiments, a method may include identifying, via a comparator, the largest among a plurality of voltage values, and powering one or more logic components within the comparator with the identified voltage value.Type: ApplicationFiled: March 21, 2013Publication date: September 25, 2014Applicant: Freescale Semiconductor, Inc.Inventors: Pedro Barbosa Zanetta, Ivan Carlos Ribeiro Nascimento
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Publication number: 20140239927Abstract: Systems and methods for transition control in a hybrid Switched-Mode Power Supply (SMPS). In some embodiments, a hybrid SMPS may include linear circuitry configured to produce an output voltage proportional to a variable duty cycle when the SMPS operates in linear mode and hysteretic circuitry coupled to the linear circuitry, the hysteretic circuitry configured to cause the duty cycle to assume one of two predetermined values when the SMPS operates in hysteretic mode. The hybrid SMPS may also include transition circuitry coupled to the linear circuitry and to the hysteretic circuitry, the transition circuitry configured to bypass at least a portion of the linear circuitry in response to the hybrid SMPS transitioning from the hysteretic mode to the linear mode.Type: ApplicationFiled: February 22, 2013Publication date: August 28, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Ivan Carlos Ribeiro Nascimento, Edevaldo Pereira Silva, JR.
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Patent number: 8599169Abstract: A touch sensing interface (101) includes a noise touch sensing circuit (110) that utilizes electromagnetic (EM) noise in a touch panel (102) to determine whether a pad of the touch panel is touched, such as by a finger of a user. The noise touch sensing circuit detects noise in a first pad (104) and in a second pad (105) of the touch panel, compares power of the noise in the first pad to power of noise in the second pad, and outputs a signal (132) indicative of the first pad being touched when power of noise in the first pad exceeds power of noise in the second pad by a pre-selected amount. The touch sensing interface may include a capacitive touch sensing circuit (120) and a controller (130) that selectively actuates the noise touch sensing circuit and the capacitive touch sensing circuit.Type: GrantFiled: December 14, 2011Date of Patent: December 3, 2013Assignee: Freescale Semiconductor, Inc.Inventor: Ivan Carlos Ribeiro Nascimento
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Publication number: 20130285734Abstract: A device (200) includes a circuit (202) and a driver stage (204) therefor. The circuit includes two sub-circuits (231 and 232). The driver stage includes switcher logic (206) that produces signals that control switching on and off of the sub-circuits. The switcher logic also produces other signals in advance of the signals that control the switching of the sub-circuits. The driver stage includes delay compensations circuits (221 and 222), coupled to the switcher logic and to the circuit, that produce timing signals for the switcher logic. The timing signals are closely aligned with moments that a changing voltage at a node between the sub-circuits passes through threshold voltages. The timing signals compensate for all delays of signals through the device such that a period that both sub-circuits are off is minimized, while ensuring that both sub-circuits are not on at a same time.Type: ApplicationFiled: April 27, 2012Publication date: October 31, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Ivan Carlos Ribeiro NASCIMENTO, Andre Luis VILAS BOAS