Patents by Inventor Ivan Fu

Ivan Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11190335
    Abstract: A method for performing pattern detection and alignment on a programmable logic device is disclosed. A word aligner unit, implemented by a hard intellectual property block, is configured to detect a plurality of control characters by recognizing a proper subset of bits that are common among the plurality of control characters. It is determined whether a predetermined number of consecutive control characters has been detected in a frame of data. A boundary location associated with a detected predetermined number of consecutive control characters from the word aligner unit is identified. The frame of data is aligned in response to the boundary location associated with the detected predetermined number of consecutive control characters.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Boon Hong Oh, Ivan Fu Sun Teh, Chee Seng Tan
  • Publication number: 20190280850
    Abstract: A receiver circuit includes a transition density detector circuit that generates a transition density signal based on a comparison between a transition density of data words to a transition density threshold. The receiver circuit also includes a bit shift and pattern detector circuit that bit shifts one of the data words to generate bit shifted data in response to the transition density signal indicating that the transition density of the data words has reached the transition density threshold. The bit shift and pattern detector circuit counts a number of bits shifts performed on the bit shifted data to locate a synchronization character. The receiver circuit also includes a word alignment circuit that bit shifts the data words by the number of bits shifts to generate word aligned data.
    Type: Application
    Filed: May 28, 2019
    Publication date: September 12, 2019
    Applicant: Intel Corporation
    Inventors: Chee Seng Tan, Boon Hong Oh, Ivan Fu Sun Teh
  • Publication number: 20190044695
    Abstract: A method for performing pattern detection and alignment on a programmable logic device is disclosed. A word aligner unit, implemented by a hard intellectual property block, is configured to detect a plurality of control characters by recognizing a proper subset of bits that are common among the plurality of control characters. It is determined whether a predetermined number of consecutive control characters has been detected in a frame of data. A boundary location associated with a detected predetermined number of consecutive control characters from the word aligner unit is identified. The frame of data is aligned in response to the boundary location associated with the detected predetermined number of consecutive control characters.
    Type: Application
    Filed: January 23, 2018
    Publication date: February 7, 2019
    Inventors: Boon Hong OH, Ivan Fu Sun TEH, Chee Seng TAN
  • Patent number: 8426253
    Abstract: An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded. An electrically-conductive housing encases the potting material and forms exterior packaging of the device. During manufacturing, the electrically-conductive structure, the die, and at least part of the lead may be arranged within the electrically-conductive housing either before or after the potting material is disposed in the housing. When the integrated circuit device is operating, heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: April 23, 2013
    Assignee: Vishay General Semiconductor LLC
    Inventors: Peter Chou, Lucy Tian, Ivan Fu, Samuel Li, May-Luen Chou
  • Patent number: 8362111
    Abstract: Stone is formed from 5 to 60% by weight of polymerised, low-viscosity, transparent or low-colour-resin, 20 to 90% by weight of spherical alumina trihidrate Al2O3.3H2O containing less regular particles containing, advantageously 0 to 100% by weight of a transparent or translucent substitute of alumina trihydrate, and/or with 0 to 20% or pre-prepared particulate, filled resin of a chosen colour, and/or mineral particles and less than 2% by weight of luminophor. These individual components are mixed intensely whilst extracting included gaseous parts. Extraction is carried out whilst mixing, and/or after mixing, and/or before mixing. The mixture is initiated by introducing a starter and intensely mixing it into the mixture. The mixture is poured into a mould or onto a moving endless belt. The cured synthetic stone is removed from the mould or the hardened composite is taken off the the belt. Synthetic stone can be used in products as a light carrier.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: January 29, 2013
    Inventors: Ivan Fu{hacek over (c)}ik, Michal Poljakov
  • Publication number: 20120252167
    Abstract: An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded. An electrically-conductive housing encases the potting material and forms exterior packaging of the device. During manufacturing, the electrically-conductive structure, the die, and at least part of the lead may be arranged within the electrically-conductive housing either before or after the potting material is disposed in the housing. When the integrated circuit device is operating, heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing.
    Type: Application
    Filed: June 11, 2012
    Publication date: October 4, 2012
    Applicant: VISHAY GENERAL SEMICONDUCTOR LLC
    Inventors: Peter Chou, Lucy Tian, Ivan Fu, Samuel Li, May-Luen Chou
  • Patent number: 8198709
    Abstract: An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded. An electrically-conductive housing encases the potting material and forms exterior packaging of the device. During manufacturing, the electrically-conductive structure, the die, and at least part of the lead may be arranged within the electrically-conductive housing either before or after the potting material is disposed in the housing. When the integrated circuit device is operating, heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: June 12, 2012
    Assignee: Vishay General Semiconductor LLC
    Inventors: Peter Chou, Lucy Tian, Ivan Fu, Samuel Li, May-Luen Chou
  • Publication number: 20080093735
    Abstract: An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded. An electrically-conductive housing encases the potting material and forms exterior packaging of the device. During manufacturing, the electrically-conductive structure, the die, and at least part of the lead may be arranged within the electrically-conductive housing either before or after the potting material is disposed in the housing. When the integrated circuit device is operating, heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing.
    Type: Application
    Filed: October 18, 2006
    Publication date: April 24, 2008
    Inventors: Peter Chou, Lucy Tian, Ivan Fu, Samuel Li, M.L. Chou