Abstract: An apparatus and method for per-user fine-grained data access security. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions associated with a plurality of jobs to generate memory access requests on behalf of a plurality of users; memory access circuitry to couple at least one core of the plurality of cores to a memory, the memory access circuitry comprising: per-user authentication circuitry operable to perform an access check for a request to access a data block in the memory at a sub-page granularity, the request comprising a security index associated with the data block; the per-user authentication circuitry to use the security index to identify corresponding bits within an access control data structure to determine whether to provide access to the data block in response to the request.

Abstract: Apparatus and method for remote virtual-to-physical address translations.

Abstract: Technology described herein provides a dynamically reconfigurable processing core. The technology includes a plurality of pipelines comprising a core, where the core is reconfigurable into one of a plurality of core modes, a core network to provide inter-pipeline connections for the pipelines, and logic to receive a morph instruction including a target core mode from an application running on the core, determine a present core state for the core, and morph, based on the present core state, the core to the target core mode. In embodiments, to morph the core, the logic is to select, based on the target core mode, which inter-pipeline connections are active, where each pipeline includes at least one multiplexor via which the inter-pipeline connections are selected to be active. In embodiments, to morph the core, the logic is further to select, based on the target core mode, which memory access paths are active.

Abstract: Embodiments of apparatuses, methods, and systems for scheduling tasks to hardware threads are described. In an embodiment, a processor includes a multiple hardware threads and a task manager. The task manager is to issue a task to a hardware thread. The task manager includes a hardware task queue to store a descriptor for the task. The descriptor is to include a field to store a value to indicate whether the task is a single task, a collection of iterative tasks, and a linked list of tasks.

Abstract: Embodiments of apparatuses, methods, and systems for a multithreaded processor core with hardware-assisted task scheduling are described. In an embodiment, a processor includes a first hardware thread, a second hardware thread, and a task manager. The task manager is to issue a task to the first hardware thread. The task manager includes a hardware task queue in which to store a plurality of task descriptors. Each of the task descriptors is to represent one of a single task, a collection of iterative tasks, and a linked list of tasks.