Patents by Inventor Ivan Herrera Mejia
Ivan Herrera Mejia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230401130Abstract: One embodiment provides an apparatus comprising a circuit board; an active interposer coupled with the circuit board via a debug package, and a graphics processor die coupled with the active interposer via the debug package. The graphics processor die includes graphics processor resources configured to execute instructions for a multi-die system on chip (SoC) device and excludes functionality that is implemented in a separate due of the multi-die SoC. The apparatus includes a field-programmable gate array (FPGA) including hardware logic that is configurable to emulate functionality provided by the separate die of the multi-die SoC device, which enables silicon validation of the graphics processor die separately from other dies of the multi-die SoC.Type: ApplicationFiled: June 14, 2022Publication date: December 14, 2023Applicant: Intel CorporationInventors: Rakesh Mehta, Hanmanthrao Patli, Ivan Herrera Mejia, Raj Chandar Rasappan, Hagay Spector, Renu Patle, Fylur Rahman Sathakathulla, Ruchira Liyanage, Raju Kasturi, Fred Steinberg, Ananth Gopalakrishnan, Satish Venkatesan, Pradyumna Reddy Patnam, Suresh Pothukuchi, Tapan Ganpule, Atthar H. Mohammed, Altug Koker
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Publication number: 20230401132Abstract: Described herein is a generic hardware/software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation. The HSC channel translates a DPI interface into a hardware FIFO based mechanism. This translation allows the reuse of the methods without having to re-implement the entire flow in pure hardware. The core logic for the transactor remains the same, while only a small layer of the transactor is converted into the FIFO based mechanism.Type: ApplicationFiled: June 14, 2022Publication date: December 14, 2023Applicant: Intel CorporationInventors: Renu Patle, Hanmanthrao Patli, Rakesh Mehta, Hagay Spector, Ivan Herrera Mejia, Fylur Rahman Sathakathulla, Gowtham Raj Karnam, Mohsin Ali, Sahar Sharabi, Abraham Halevi Fraenkel, Eyal Pniel, Ehud Cohn, Raghav Ramesh Lakshmi, Altug Koker
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Patent number: 10401928Abstract: Embodiments including systems, methods, and apparatuses associated providing an interface between a north complex and a south complex of a system on a chip (SoC). In embodiments, the north complex may include a microcontroller in an input signal requirement. A power-on control block may be coupled with the microcontroller, and the power-on control block may be configured to receive a control signal from a component of the south complex, and alter the control signal based at least in part on the input signal requirement of the microcontroller.Type: GrantFiled: March 9, 2017Date of Patent: September 3, 2019Assignee: INTEL CORPORATIONInventors: Ivan Herrera Mejia, Zeev Offen
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Patent number: 9798369Abstract: An integrated circuit such as a SoC may indicate the critical battery status without powering-on a substantial portion including the host processing cores. The SoC may include a microcontroller, which may cause the critical battery status data to be stored in a static memory and the display unit may retrieve such data from the static memory to display a visual symbol on the screen. The other portions of the SoC such as the dynamic memory, system agent, media processors, and memory controller hubs may be powered-down while the critical battery status is displayed in the visual form on the screen.Type: GrantFiled: March 24, 2016Date of Patent: October 24, 2017Assignee: Intel CorporationInventors: Ivan Herrera Mejia, Kenneth D. Shoemaker, Ryan D. Wells
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Patent number: 9785604Abstract: Methods and apparatus for utilization of preset evaluation to improve input/output performance in high-speed serial interconnects are described. In some embodiments, performance of a link is evaluated at a plurality of equalization values and one of the plurality of equalization values is selected for the link based on comparison of a plurality of margin values that are to be determined for each of the plurality of equalization values. Other embodiments are also claimed and/or disclosed.Type: GrantFiled: February 15, 2013Date of Patent: October 10, 2017Assignee: Intel CorporationInventors: Ivan Herrera Mejia, Manuel A. Aguilar Arreola, Shrinivas Venkatraman, Andrea R. Vavra, Pavel Konev
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Publication number: 20170242708Abstract: Embodiments including systems, methods, and apparatuses associated providing an interface between a north complex and a south complex of a system on a chip (SoC). In embodiments, the north complex may include a microcontroller in an input signal requirement. A power-on control block may be coupled with the microcontroller, and the power-on control block may be configured to receive a control signal from a component of the south complex, and alter the control signal based at least in part on the input signal requirement of the microcontroller.Type: ApplicationFiled: March 9, 2017Publication date: August 24, 2017Inventors: Ivan Herrera Mejia, Zeev Offen
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Patent number: 9594413Abstract: Embodiments including systems, methods, and apparatuses associated providing an interface between a north complex and a south complex of a system on a chip (SoC). In embodiments, the north complex may include a microcontroller in an input signal requirement. A power-on control block may be coupled with the microcontroller, and the power-on control block may be configured to receive a control signal from a component of the south complex, and alter the control signal based at least in part on the input signal requirement of the microcontroller.Type: GrantFiled: December 24, 2013Date of Patent: March 14, 2017Assignee: Intel CorporationInventors: Ivan Herrera Mejia, Zeev Offen
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Patent number: 9436244Abstract: Methods and apparatus related to adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications are described. In some embodiments, a first bit pattern is detected, at a first agent, that indicates a speculative entry by a second agent into a low power consumption state and one or more control loops are frozen. A second bit pattern is detected (after entering the low power consumption state) that indicates exit from the low power consumption state by the second agent and the one or more control loops are unfrozen (e.g., in a specific order). Other embodiments are also claimed and/or disclosed.Type: GrantFiled: March 15, 2013Date of Patent: September 6, 2016Assignee: Intel CorporationInventors: Yun He, Narender R. Nagulapally, Sanjib Sarkar, Ivan Herrera Mejia, Ruchira K. Liyanage
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Publication number: 20160202746Abstract: An integrated circuit such as a SoC may indicate the critical battery status without powering-on a substantial portion including the host processing cores. The SoC may include a microcontroller, which may cause the critical battery status data to be stored in a static memory and the display unit may retrieve such data from the static memory to display a visual symbol on the screen. The other portions of the SoC such as the dynamic memory, system agent, media processors, and memory controller hubs may be powered-down while the critical battery status is displayed in the visual form on the screen.Type: ApplicationFiled: March 24, 2016Publication date: July 14, 2016Inventors: Ivan Herrera Mejia, Kenneth D. Shoemaker, Ryan D. Wells
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Patent number: 9384351Abstract: Technologies for implementing a secure boot using multiple firmware sources are described. One or more fuses of a processing device can be configured. Based on such configuration, one or more keys can be generated. Based on the configuration of the various fuses, an operation of a firmware device can be initiated. Using the generated key(s), a protected section of the firmware device can be accessed.Type: GrantFiled: March 15, 2013Date of Patent: July 5, 2016Assignee: Intel CorporationInventors: Ivan Herrera Mejia, Kenneth D. Shoemaker
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Patent number: 9335808Abstract: An integrated circuit such as a SoC may indicate the critical battery status without powering-on a substantial portion including the host processing cores. The SoC may include a microcontroller, which may cause the critical battery status data to be stored in a static memory and the display unit may retrieve such data from the static memory to display a visual symbol on the screen. The other portions of the SoC such as the dynamic memory, system agent, media processors, and memory controller hubs may be powered-down while the critical battery status is displayed in the visual form on the screen.Type: GrantFiled: March 8, 2013Date of Patent: May 10, 2016Assignee: Intel CorporationInventors: Ivan Herrera Mejia, Kenneth D. Shoemaker, Ryan D. Wells
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Patent number: 9223365Abstract: A system, semiconductor device and method for providing a controlled system reset sequence with lower power consumption without dependency on fuses, PLL's and external XTAL's. A method to simplify a boot sequence by using a ring oscillator that compensates for voltage and temperature variations while also removing the dependency on parallel fuses, PLL's and external XTAL's.Type: GrantFiled: March 16, 2013Date of Patent: December 29, 2015Assignee: Intel CorporationInventors: Ivan Herrera Mejia, Vishram Sarurkar, Vijay K. Vuppaladadium
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Publication number: 20150177801Abstract: Embodiments including systems, methods, and apparatuses associated providing an interface between a north complex and a south complex of a system on a chip (SoC). In embodiments, the north complex may include a microcontroller in an input signal requirement. A power-on control block may be coupled with the microcontroller, and the power-on control block may be configured to receive a control signal from a component of the south complex, and alter the control signal based at least in part on the input signal requirement of the microcontroller.Type: ApplicationFiled: December 24, 2013Publication date: June 25, 2015Inventors: Ivan Herrera Mejia, Zeev Offen
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Publication number: 20140281668Abstract: Methods and apparatus related to adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications are described. In some embodiments, a first bit pattern is detected, at a first agent, that indicates a speculative entry by a second agent into a low power consumption state and one or more control loops are frozen. A second bit pattern is detected (after entering the low power consumption state) that indicates exit from the low power consumption state by the second agent and the one or more control loops are unfrozen (e.g., in a specific order). Other embodiments are also claimed and/or disclosed.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Yun He, Narender R. Nagulapally, Sanjib Sarkar, Ivan Herrera Mejia, Ruchira K. Liyanage
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Publication number: 20140281456Abstract: Technologies for implementing a secure boot using multiple firmware sources are described. One or more fuses of a processing device can be configured. Based on such configuration, one or more keys can be generated. Based on the configuration of the various fuses, an operation of a firmware device can be initiated. Using the generated key(s), a protected section of the firmware device can be accessed.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Ivan Herrera Mejia, Kenneth D. Shoemaker
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Publication number: 20140281641Abstract: A system, semiconductor device and method for providing a controlled system reset sequence with lower power consumption without dependency on fuses, PLL's and external XTAL's. A method to simplify a boot sequence by using a ring oscillator that compensates for voltage and temperature variations while also removing the dependency on parallel fuses, PLL's and external XTAL's.Type: ApplicationFiled: March 16, 2013Publication date: September 18, 2014Applicant: Intel CorporationInventors: Ivan Herrera Mejia, Vishram Sarurkar, Vijay K. Vuppaladadium
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Publication number: 20140258698Abstract: An integrated circuit such as a SoC may indicate the critical battery status without powering-on a substantial portion including the host processing cores. The SoC may include a microcontroller, which may cause the critical battery status data to be stored in a static memory and the display unit may retrieve such data from the static memory to display a visual symbol on the screen. The other portions of the SoC such as the dynamic memory, system agent, media processors, and memory controller hubs may be powered-down while the critical battery status is displayed in the visual form on the screen.Type: ApplicationFiled: March 8, 2013Publication date: September 11, 2014Inventors: Ivan Herrera Mejia, Kenneth D. Shoemaker, Ryan D. Wells
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Publication number: 20140237301Abstract: Methods and apparatus for utilization of preset evaluation to improve input/output performance in high-speed serial interconnects are described. In some embodiments, performance of a link is evaluated at a plurality of equalization values and one of the plurality of equalization values is selected for the link based on comparison of a plurality of margin values that are to be determined for each of the plurality of equalization values. Other embodiments are also claimed and/or disclosed.Type: ApplicationFiled: February 15, 2013Publication date: August 21, 2014Inventors: Ivan Herrera Mejia, Manuel A. Aguilar Arreola, Shrinivas Venkatraman, Andrea R. Vavra, Pavel Konev
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Patent number: 8112265Abstract: In general, in one aspect, the disclosure describes creation of a randomization list that includes only a subset of the logic states of an integrated circuit (IC). The subset being selectable by signal so as to define logic states that can be randomized for specific events. The randomization list is during simulation to randomize the logic states defined therein to simulate a specific event occurring during operation of the IC. For example, the randomization list may include those signals that can be randomized upon exiting from a powered down state (e.g., deep power down, C6). The signals that can be randomized may be defined by excluding the signals that cannot be randomized (those still receiving power in the C6 mode). The contents of registers of the IC can be confirmed after the randomization and exit from the C6 mode.Type: GrantFiled: December 31, 2008Date of Patent: February 7, 2012Assignee: Intel CorporationInventors: Maulik Joshi, Ivan Herrera Mejia, Joshua D. Louie
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Publication number: 20100169065Abstract: In general, in one aspect, the disclosure describes creation of a randomization list that includes only a subset of the logic states of an integrated circuit (IC). The subset being selectable by signal so as to define logic states that can be randomized for specific events. The randomization list is during simulation to randomize the logic states defined therein to simulate a specific event occurring during operation of the IC. For example, the randomization list may include those signals that can be randomized upon exiting from a powered down state (e.g., deep power down, C6). The signals that can be randomized may be defined by excluding the signals that cannot be randomized (those still receiving power in the C6 mode). The contents of registers of the IC can be confirmed after the randomization and exit from the C6 mode.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: Maulik Joshi, Ivan Herrera Mejia, Joshua D. Louie