Abstract: Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of devices by providing for an interface having inputs and/or outputs that are adjustably delayed. This allows embodiments of the present invention to sense the signal delay and utilize adjustable input or output delays to correct the signal timing relationships such that correctly timed communication signals are received by the internal circuitry of the device. In one embodiment of the present invention, a register is utilized to adjust the timing delay of individual input and/or output signals for the device. This increases the robustness of the device and its resistance to communication or data corruption, allowing larger ranges of environmental conditions and input capacitances of systems or communication busses to be tolerated.

Abstract: Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of devices by providing for an interface having inputs and/or outputs that are adjustably delayed. This allows embodiments of the present invention to sense the signal delay and utilize adjustable input or output delays to correct the signal timing relationships such that correctly timed communication signals are received by the internal circuitry of the device. In one embodiment of the present invention, a register is utilized to adjust the timing delay of individual input and/or output signals for the device. This increases the robustness of the device and its resistance to communication or data corruption, allowing larger ranges of environmental conditions and input capacitances of systems or communication busses to be tolerated.

Abstract: Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of devices by providing for an interface having inputs and/or outputs that are adjustably delayed. This allows embodiments of the present invention to sense the signal delay and utilize adjustable input or output delays to correct the signal timing relationships such that correctly timed communication signals are received by the internal circuitry of the device. In one embodiment of the present invention, a register is utilized to adjust the timing delay of individual input and/or output signals for the device. This increases the robustness of the device and its resistance to communication or data corruption, allowing larger ranges of environmental conditions and input capacitances of systems or communication busses to be tolerated.

Abstract: A planetary device for feeding electrode wiring in welding operations is provided with a housing through which the wire is fed, the central portion of the housing being shaped as a flange with a hub, and the front side thereof being provided with seats housing pistons bearing radially adjustable wire-feeding rollers. The piston heads are in constant contact with the shorter arms of bow-type double-armed levers hingedly affixed to the flange portion of the hub and located perpendicularly to the axis of the electrode wire fed through the housing. The longer arms of the levers contact the surfaces of a cam supported in the hub of the housing for rotation with respect thereto. A torque spring in the form of an Archimedes spiral, disposed between the flange of the housing and the cam, and having its respective inner and outer ends affixed to such members, constantly urges the cam with respect to the housing in such direction as to urge the rollers inwardly into engagement with the electrode wire.