Abstract: A clock selection circuit which selects and enables one of a plurality of clock circuits in response to initialization by a processing unit or detection of failure of an on-line clock circuit. The clock circuits are selected on the basis of a priority arrangement. The clock circuit failure is detected by a retriggerable monostable multivibrator and the selection priority is based on time delays generated by programmed counters associated with each clock circuit.

Abstract: A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.

Abstract: A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.

Abstract: A frequency disturbance minimization circuit for use in a phase locked loop circuit. A pulse generator eliminates random phase shift, which occurs after a reference clock outage, by synchronizing counted down derivatives of the local and reference clock circuits. A window circuit provides a signal representative of the difference in phase between these local and reference clock circuits. A counter accumulates these phase difference window signals for periodic interrogation by a microprocessor which causes a voltage controlled oscillator to adjust its frequency in the direction necessary to eliminate this phase difference.

Abstract: A circuit which controls the selection and activation of one of a plurality of clock circuits arranged in copies. Selection circuitry is used to detect failure of an on-line clock circuit, scan a plurality of available clock circuits in a predetermined sequence and place the next available properly operating clock circuit on line. Control circuitry prevents erroneous clock selection during power-up/power down operations and enables predetermined clock circuit copies to be disabled.

Abstract: A clock synchronization system for use in a digital switching system including multiple clock circuits. This circuit includes multiple synchronization circuits connected in a master-slave arrangement. Each synchronization circuit includes a counter chain which provides a periodic system framing pulse and a trigger circuit which insures that its slave system framing pulse is in synchronization with the master system framing pulse.