Abstract: Various implementations described herein are directed to a device having alarm circuitry that receives a clock signal and provides alarm chain signals based on the clock signal. The device may include delay chain circuitry that receives the alarm chain signals from the alarm circuitry and provides delay chain signals. The device may include output circuitry that receives the delay chain signals from the delay chain circuitry and provides an alarm control signal based on the delay chain signals.

Abstract: Various implementations described herein are directed to a device having alarm circuitry that receives a clock signal and provides alarm chain signals based on the clock signal. The device may include delay chain circuitry that receives the alarm chain signals from the alarm circuitry and provides delay chain signals. The device may include output circuitry that receives the delay chain signals from the delay chain circuitry and provides an alarm control signal based on the delay chain signals.

Abstract: An apparatus has an input interface for receiving an input clock signal, and a plurality N of clock divider circuits, each clock divider circuit generating a corresponding monitored clock signal by dividing the input clock signal by N. Each clock divider circuit is arranged, when generating a leading edge of each clock cycle of its corresponding monitored clock signal, to use a leading edge of a different clock cycle of the input clock signal to the clock cycle of the input clock signal used by any other of the clock divider circuits. Analysis circuitry provided in association with each clock divider circuit produces a width indication for each clock cycle of the corresponding monitored clock signal. Alarm generation circuitry then triggers an alarm signal when, for any of the monitored clock signals, a variation in the width indication is detected over multiple clock cycles of that monitored clock signal.

Abstract: A computer implemented system and method is provided for modifying a layout of one or more standard cells defining a circuit component, the layout providing a layout pattern for a process technology. The method comprises receiving, after completion of one or more initial place and route operations, an input data file that includes the layout pattern of the layout. The layout includes the one or more standard cells and placement and routing information generated by the one or more initial place and route operations. The method further comprises identifying one or more metal portions associated with one or more rails of the one or more standard cells of the layout. A metal fill operation is then performed using the input data file in order to generate a modified input data file. The metal fill operation includes modifying the one or more metal portions with one or more metal fill patterns to form a reduced resistive path associated with the one or more metal portions.

Abstract: A computer implemented system and method is provided for modifying a layout of one or more standard cells defining a circuit component, the layout providing a layout pattern for a process technology. The method comprises receiving, after completion of one or more initial place and route operations, an input data file that includes the layout pattern of the layout. The layout includes the one or more standard cells and placement and routing information generated by the one or more initial place and route operations. The method further comprises identifying one or more metal portions associated with one or more rails of the one or more standard cells of the layout. A metal fill operation is then performed using the input data file in order to generate a modified input data file. The metal fill operation includes modifying the one or more metal portions with one or more metal fill patterns to form a reduced resistive path associated with the one or more metal portions.