Patents by Inventor Ivan Milosavljevic

Ivan Milosavljevic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220137510
    Abstract: A method, apparatus, and system for processing a material stack. A hydrogen silsesquioxane layer is deposited on the material stack. A diffusion barrier layer is deposited on the hydrogen silsesquioxane layer to form a bilayer. The diffusion barrier layer comprises a material having a thickness that increases an amount of time before the hydrogen silsesquioxane layer ages to change a dose in an electron beam needed to expose the hydrogen silsesquioxane layer for a selected feature geometry with a desired width. The electron beam is directed through a surface of the bilayer to form an exposed portion of the bilayer. The electron beam applies the dose that is selected based on a pattern density of features for the material stack to have a desired level of exposure of the hydrogen silsesquioxane layer for the selected feature geometry. The hydrogen silsesquioxane layer is developed. The exposed portion remains on material stack.
    Type: Application
    Filed: October 25, 2021
    Publication date: May 5, 2022
    Inventors: Antonio Mei, Ivan Milosavljevic, Amanda Simpson
  • Publication number: 20190383927
    Abstract: The present invention relates to a gesture detection Apparatus and Method of Operation comprising of an mm-wave radar sensor, having an integrated mm-wave IC front end, with special arrangement of the antenna system, with a new art of angle detection and which does not contain radio down-conversion topology, common in non-professional radar systems. The proposed Apparatus is capable of detecting the two dimensional target angle, having an inherently low-cost system topology, suitable as a replacement in functionality for the commonly used gesture detection system in consumer applications. The proposed apparatus topology consist of two transmitting planar antennae, and two pairs of receiving antennae without the down-conversion of receiver chains, but with introduced analog signal combining structures and mm-wave power detectors. The complete proposed sensor apparatus topology with integrated antennae, mm-wave IC and digital processing parts may be realized in a module smaller than 1×1×0.
    Type: Application
    Filed: January 26, 2016
    Publication date: December 19, 2019
    Applicant: NOVELIC D.O.O.
    Inventors: Veljko MIHAJLOVIC, Veselin BRANKOVIC, Dusan KRCUM, Ivan MILOSAVLJEVIC, Darko TASOVAC, Marko PARAUSIC, Dorde GLAVONJIC
  • Publication number: 20180164429
    Abstract: The present invention relates to a parking support Apparatus and Method of operation comprising of an mm-wave radar sensor, having an integrated mm-wave IC front end. The proposed Apparatus is capable of detecting the parking obstacle object distance and angle, having inherently low cost system topology, suitable as a replacement in functionality for the commonly used ultrasound sensors. The proposed apparatus topology consist of one transmitting and two planar antennae, mm-wave radar topology with one down conversion chain and one transmitter chain based on FMCW radar, CW radar and Doppler radar, analog combining circuitry and N mm-wave power detectors, where N takes integer values from 1 and larger. The specific proposed method of operation is adjusted to a dedicated application. A combination of more than one proposed apparatus enables smart observation of the parking area in front of the moving platform with wired or wireless connection to the information evaluation and control entity.
    Type: Application
    Filed: June 17, 2015
    Publication date: June 14, 2018
    Applicant: NOVELIC D.O.O.
    Inventors: Darko TASOVAC, Veljko MIHAJLOVIC, Veselin BRANKOVIC, Dusan KRCUM, Ivan MILOSAVLJEVIC
  • Patent number: 8980759
    Abstract: A method of forming a slanted field plate including forming epitaxy for a FET on a substrate, forming a wall near a drain of the FET, the wall comprising a first negative tone electron-beam resist (NTEBR), depositing a dielectric over the epitaxy and the wall, the wall causing the dielectric to have a step near the drain of the FET, depositing a second NTEBR over the dielectric, wherein surface tension causes the deposited second NTEBR to have a slanted top surface between the step and a source of the FET, etching anisotropically vertically the second NTEBR and the dielectric to remove the second NTEBR and to transfer a shape of the slanted top surface to the dielectric, and forming a gatehead comprising metal on the dielectric between the step and the source of the FET, wherein the gatehead forms a slanted field plate.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: March 17, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Andrea Corrion, Joel C. Wong, Keisuke Shinohara, Miroslav Micovic, Ivan Milosavljevic, Dean C. Regan, Yan Tang
  • Patent number: 8698201
    Abstract: A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer and a barrier layer over the channel layer includes forming a gate of a first dielectric, forming first sidewalls of a second dielectric on either side and adjacent to the gate, selectively etching into the buffer layer to form a mesa for the field effect transistor, depositing a dielectric layer over the mesa, planarizing the dielectric layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the dielectric layer over the mesa are on the same planarized surface, depositing metal on the planzarized surface, annealing to form the gate into a metal silicided gate, and etching to remove excess non-silicided metal.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: April 15, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Dean C. Regan, Keisuke Shinohara, Andrea Corrion, Ivan Milosavljevic, Miroslav Micovic, Peter J. Willadsen, Colleen M. Butler, Hector L. Bracamontes, Bruce T. Holden, David T. Chang
  • Patent number: 8558281
    Abstract: A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer and a barrier layer over the channel layer includes forming a gate including silicon, forming first sidewalls of a first material on either side and adjacent to the gate, selectively etching into the buffer layer to form a mesa for the field effect transistor, depositing a material layer over the mesa, planarizing the material layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the material layer over the mesa are on the same planarized surface, depositing metal on the planzarized surface, annealing to form the gate into a metal silicided gate, and etching to remove excess non-silicided metal.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: October 15, 2013
    Assignee: HRL Laboratories, LLC
    Inventors: Dean C. Regan, Keisuke Shinohara, Andrea Corrion, Ivan Milosavljevic, Miroslav Micovic, Peter J. Willadsen, Colleen M. Butler, Hector L. Bracamontes, Bruce T. Holden, David T. Chang
  • Patent number: 8039903
    Abstract: In various embodiments, a tiered gate structure transistor is provided including a source, a drain, and a gate between the source and the drain. The tiered gate structure transistor including a gate foot having a top portion and sidewalls. A gate head is attached to the top portion of the gate foot. A passivation layer extends along and directly contacts an uppermost surface of the source, and extends along and directly contacts an uppermost surface of the drain, the passivation layer surrounds the sidewalls of the gate foot such that the top portion is not covered by the passivation layer and such that the passivation layer surrounding the sidewalls supports the gate head.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: October 18, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: Ivan Milosavljevic, Adele Schmitz, Michael Antcliffe, Ming Hu, Lorna Hodgson
  • Patent number: 7804114
    Abstract: In one embodiment, a tiered gate device is provided including a source, a drain, and a gate foot therebetween. A gate head is attached to the gate foot. A source extension extends from on an uppermost surface of the source toward the gate foot along the substrate. In some embodiments a drain extension extends from on and uppermost surface of the drain toward the gate foot along the substrate.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: September 28, 2010
    Assignee: HRL Laboratories, LLC
    Inventors: Ivan Milosavljevic, Adele Schmitz, Michael Antcliffe, Ming Hu
  • Patent number: 7723761
    Abstract: In one embodiment, a tiered gate structure is provided having a substrate including a source, a drain and a gate thereon. The gate includes an elongated gate foot having a first deposition gate material extending from the substrate, the elongated gate foot having a top portion distal from the substrate. The gate head has a second deposition gate material and includes an elongated portion extending downward from the gate head to connect to the top portion of the elongated gate foot.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: May 25, 2010
    Assignee: HRL Laboratories, LLC
    Inventors: Ivan Milosavljevic, Adele Schmitz, Michael Delaney, Michael Antcliffe
  • Patent number: 7608497
    Abstract: A method for fabricating a tiered structure includes forming a gate on a semiconductor substrate. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening through it to define the gate foot over the substrate. After forming the gate foot, the gate foot mask is stripped and a passivation layer is formed over the gate foot and the substrate. A gate head mask is formed over the gate foot with the gate head mask exposing a portion of the passivation layer on a top portion of the gate foot. The portion of the passivation layer on the top portion of the gate foot is removed to expose the top portion of the gate foot. A gate head is formed on the top portion of the gate foot using the gate head mask. A lift-off process is performed, removing the gate head mask.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: October 27, 2009
    Inventors: Ivan Milosavljevic, Adele Schmitz, Michael Antcliffe, Ming Hu, Lorna Hodgson
  • Patent number: 7534672
    Abstract: In one embodiment, a tiered gate device is provided including a source, a drain, and a gate foot therebetween. A gate head is attached to the gate foot. A source extension extends from on the source toward the gate foot along the substrate. In some embodiments a drain extension extends from on the drain toward the gate foot along the substrate.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: May 19, 2009
    Assignee: HRL Laboratories, LLC
    Inventors: Ivan Milosavljevic, Adele Schmitz, Michael Antcliffe, Ming Hu
  • Patent number: 7439166
    Abstract: In one implementation, a method for fabricating a tiered structure is provided, which includes forming a source and a drain on a substrate with a gate formed therebetween. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening through it to define the gate foot over the substrate. After forming the gate foot, the gate foot mask is stripped. A gate head mask is formed over the gate foot with the gate head mask exposing a top portion of the gate foot. A gate head is formed on the top portion of the gate foot using the gate head mask. A lift-off process is performed, removing the gate head mask.
    Type: Grant
    Filed: June 11, 2005
    Date of Patent: October 21, 2008
    Assignee: HRL Laboratories, LLC
    Inventors: Ivan Milosavljevic, Adele Schmitz, Michael Delaney, Michael Antcliffe
  • Publication number: 20010047623
    Abstract: The invention relates to a method of combustion, in which waste, especially household and/or industrial waste, is subjected to a process (T) comprising at least one step in which the waste is pyrolysed and a gas mixture containing hydrocarbons is created, and then a step in which gaseous hydrocarbons are brought into contact with steam and with an oxidizing agent, and resulting in the production of a final gas mixture (FM) containing carbon monoxide and hydrogen, and then at least part of the carbon monoxide and of the hydrogen is used, as a mixture, as fuel, for example in a blast furnace (F) or in a cement kiln.
    Type: Application
    Filed: November 15, 1999
    Publication date: December 6, 2001
    Inventors: IVAN MILOSAVLJEVIC, PASCAL DUPERRAY, STEPHANE ARNOUX
  • Patent number: 6318278
    Abstract: In this process the material is passed through a precalcination device equipped with at least one fuel injector at the outlet of which a fuel injection zone is formed, then the at least partially calcined material is passed into the rotary kiln which at its downstream end, is equipped with a primary combustion unit. At least one oxygen rich fluid with an oxygen concentration by volume higher than that of the products of combustion from the rotary kiln is injected near to the injection zone so that the oxygen rich fluid can supply from 1% to 40%, and preferably form 1 to 10% of the stoichiometric amount of oxygen needed for the combustion of the fuel injected by the injector.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: November 20, 2001
    Assignee: L'Air Liquide, Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges Claude
    Inventors: Jacques Dugue, Thierry Borissoff, Ovidiu Marin, Ivan Milosavljevic, Dora Sophia Alves, Michel Viardot