Patents by Inventor Ivan Miro Panades
Ivan Miro Panades has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11146278Abstract: The invention concerns a frequency locked loop comprising: a digitally controlled oscillator (102) configured to generate a frequency signal (F); a frequency counter (310) configured to generate an estimate (f_EST) of the frequency of the frequency signal based on a reference clock signal (CLK_REF); and a controller (314) configured to generate a digital control signal (C_FREQ) for controlling the digitally controlled oscillator based on the estimated frequency, wherein the controller is clocked by a further clock signal (CLK) having a variable frequency, and the controller is configured to generate a trigger signal (AUTO_CLEAR) for triggering a counting phase of the frequency counter.Type: GrantFiled: November 27, 2018Date of Patent: October 12, 2021Assignee: Commissariat à l'Energie Atomique et aux Energies AlternativesInventor: Ivan Miro Panades
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Patent number: 10680963Abstract: A receiving circuit of a communications link comprises: a first data buffer configured to input, under control of a first clock signal, data of a first data stream transmitted by a transmitting circuit, and to generate a credit trigger signal indicating when a data value is read from the first data buffer, wherein data is read from the first data buffer, or from a further data buffer coupled to the output of the first data buffer, under control of a second clock signal; and a credit generation circuit configured to generate, based on the credit trigger signal, a credit signal for transmission to the transmitting circuit under control of the first clock signal, the credit signal indicating that one or more further data values of the first data stream can be transmitted by the transmitting circuit.Type: GrantFiled: July 6, 2017Date of Patent: June 9, 2020Assignee: Commissariat à l'Energie Atomique et aux Energies AlternativesInventor: Ivan Miro Panades
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Patent number: 10454486Abstract: The invention concerns a circuit comprising: a voltage generator adapted to generate a variable supply voltage for powering a processing core; a frequency generator adapted to generate a variable frequency clock signal of the processing core and comprising a frequency locked loop having: a digitally controlled oscillator configured to generate the variable frequency clock signal; and a controller (614) configured to generate a digital control signal (C_FREQ), wherein the controller is configured to implement a frequency transition of the variable frequency clock signal from a first frequency to a second lower frequency by generating: a first value of the digital control signal (C_FREQ) to apply a first reduction in the frequency of the variable frequency clock signal to a third frequency lower than the second frequency; and further values of the digital control signal (C_FREQ).Type: GrantFiled: September 18, 2018Date of Patent: October 22, 2019Assignee: COMMISSARIAT ÀL'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventor: Ivan Miro Panades
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Patent number: 10354029Abstract: A method of circuit conception including performing static timing analysis on a circuit design to identify a first subset of the synchronous devices having at least one input path with a slack time below a first threshold; simulating the circuit design using one or more functional test patterns to identify a second subset of the synchronous devices for which the number of activations during the simulation is above a second threshold; selecting at least one synchronous device forming part of both of the first and second subsets; and modifying the circuit design to include, for each selected synchronous device, a detection circuit coupled to one or more inputs of the selected synchronous device.Type: GrantFiled: December 2, 2016Date of Patent: July 16, 2019Assignee: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventor: Ivan Miro Panades
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Publication number: 20190165797Abstract: The invention concerns a frequency locked loop comprising: a digitally controlled oscillator (102) configured to generate a frequency signal (F); a frequency counter (310) configured to generate an estimate (f_EST) of the frequency of the frequency signal based on a reference clock signal (CLK_REF); and a controller (314) configured to generate a digital control signal (C_FREQ) for controlling the digitally controlled oscillator based on the estimated frequency, wherein the controller is clocked by a further clock signal (CLK) having a variable frequency, and the controller is configured to generate a trigger signal (AUTO_CLEAR) for triggering a counting phase of the frequency counter.Type: ApplicationFiled: November 27, 2018Publication date: May 30, 2019Inventor: Ivan MIRO PANADES
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Publication number: 20190089363Abstract: The invention concerns a circuit comprising: a voltage generator adapted to generate a variable supply voltage for powering a processing core; a frequency generator adapted to generate a variable frequency clock signal of the processing core and comprising a frequency locked loop having: a digitally controlled oscillator configured to generate the variable frequency clock signal; and a controller (614) configured to generate a digital control signal (C_FREQ), wherein the controller is configured to implement a frequency transition of the variable frequency clock signal from a first frequency to a second lower frequency by generating: a first value of the digital control signal (C_FREQ) to apply a first reduction in the frequency of the variable frequency clock signal to a third frequency lower than the second frequency; and further values of the digital control signal (C_FREQ).Type: ApplicationFiled: September 18, 2018Publication date: March 21, 2019Inventor: Ivan MIRO PANADES
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Patent number: 10103817Abstract: An optical receiver adapted to convert a received optical signal into a phase change of a timing signal to generate a first modified timing signal and to generate a data signal by comparing the first modified timing signal with a reference signal.Type: GrantFiled: December 16, 2016Date of Patent: October 16, 2018Assignee: Commissariat à L'Énergie Atomique et aux Énergies AlternativesInventors: Robert Polster, Ivan Miro Panades, Yvain Thonnart
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Patent number: 10090992Abstract: A clock receiver including: a ring oscillator adapted to generate a clock signal, the ring oscillator having a sequence of N inverters, an input of a first inverter being coupled to a feedback node, an input of a second inverter being connected to an output of the first inverter and to an input line for receiving a reference clock signal, and an output of the second inverter or of a third inverter providing a first phase signal; a further sequence of inverters, an input of a first further inverter being coupled to the feedback node, and an output of another further inverter providing a second phase signal; and a control circuit for adjusting an oscillation frequency of the ring oscillator based on the relative phases of the first and second phase signals.Type: GrantFiled: March 31, 2016Date of Patent: October 2, 2018Assignee: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Robert Polster, José-Luis Gonzalez Jimenez, Ivan Miro Panades
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Patent number: 10090995Abstract: A data reception device comprises: a first data input for receiving a first data signal and a clock input for receiving a clock signal; and a stability detection circuit adapted to generate: a first error signal indicating when a data transition of the first data signal occurs during a first period at least partially before a first significant clock edge of the clock signal; and a second error signal indicating when a data transition of the first data signal occurs during a second period at least partially after the first significant clock edge of the clock signal; and a control circuit configured to generate a control signal for adjusting the sampling time of the first data signal based on said first and second error signals.Type: GrantFiled: July 6, 2017Date of Patent: October 2, 2018Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventor: Ivan Miro Panades
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Publication number: 20180013545Abstract: A data reception device comprises: a first data input for receiving a first data signal and a clock input for receiving a clock signal; and a stability detection circuit adapted to generate: a first error signal indicating when a data transition of the first data signal occurs during a first period at least partially before a first significant clock edge of the clock signal; and a second error signal indicating when a data transition of the first data signal occurs during a second period at least partially after the first significant clock edge of the clock signal; and a control circuit configured to generate a control signal for adjusting the sampling time of the first data signal based on said first and second error signals.Type: ApplicationFiled: July 6, 2017Publication date: January 11, 2018Inventor: Ivan MIRO PANADES
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Publication number: 20180013689Abstract: A receiving circuit of a communications link comprises: a first data buffer configured to input, under control of a first clock signal, data of a first data stream transmitted by a transmitting circuit, and to generate a credit trigger signal indicating when a data value is read from the first data buffer, wherein data is read from the first data buffer, or from a further data buffer coupled to the output of the first data buffer, under control of a second clock signal; and a credit generation circuit configured to generate, based on the credit trigger signal, a credit signal for transmission to the transmitting circuit under control of the first clock signal, the credit signal indicating that one or more further data values of the first data stream can be transmitted by the transmitting circuit.Type: ApplicationFiled: July 6, 2017Publication date: January 11, 2018Inventor: Ivan MIRO PANADES
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Patent number: 9823301Abstract: A method is presented for characterizing a digital circuit for determining an optimum operating point of the digital circuit. The digital circuit includes sequential elements; conducting data paths; a clock tree; a time fault sensor receiving as input a data signal and configured to detect during a detection window a transition of the data signal; and a system for setting first and second operating parameters of the circuit. The method includes a) activating a conducting data path leading to the sequential element coupled to the sensor; b) determining, for a given value of the first parameter, a first value of the second parameter from which the sensor detects a transition of the data signal during the detection window, the values of the first and second parameters defining an operating point of the circuit; and c) correcting the operating point.Type: GrantFiled: February 9, 2015Date of Patent: November 21, 2017Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVESInventor: Ivan Miro Panades
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Publication number: 20170180056Abstract: An optical receiver adapted to convert a received optical signal into a phase change of a timing signal to generate a first modified timing signal and to generate a data signal by comparing the first modified timing signal with a reference signal.Type: ApplicationFiled: December 16, 2016Publication date: June 22, 2017Applicant: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Robert Polster, Ivan Miro Panades, Yvain Thonnart
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Publication number: 20170161416Abstract: A method of circuit conception including performing static timing analysis on a circuit design to identify a first subset of the synchronous devices having at least one input path with a slack time below a first threshold; simulating the circuit design using one or more functional test patterns to identify a second subset of the synchronous devices for which the number of activations during the simulation is above a second threshold; selecting at least one synchronous device forming part of both of the first and second subsets; and modifying the circuit design to include, for each selected synchronous device, a detection circuit coupled to one or more inputs of the selected synchronous device.Type: ApplicationFiled: December 2, 2016Publication date: June 8, 2017Applicant: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventor: Ivan Miro Panades
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Publication number: 20160349316Abstract: A method is presented for characterizing a digital circuit for determining an optimum operating point of the digital circuit. The digital circuit includes sequential elements; conducting data paths; a clock tree; a time fault sensor receiving as input a data signal and configured to detect during a detection window a transition of the data signal; and a system for setting first and second operating parameters of the circuit. The method includes a) activating a conducting data path leading to the sequential element coupled to the sensor; b) determining, for a given value of the first parameter, a first value of the second parameter from which the sensor detects a transition of the data signal during the detection window, the values of the first and second parameters defining an operating point of the circuit; and c) correcting the operating point.Type: ApplicationFiled: February 9, 2015Publication date: December 1, 2016Inventor: Ivan MIRO PANADES
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Publication number: 20160294540Abstract: A clock receiver including: a ring oscillator adapted to generate a clock signal, the ring oscillator having a sequence of N inverters, an input of a first inverter being coupled to a feedback node, an input of a second inverter being connected to an output of the first inverter and to an input line for receiving a reference clock signal, and an output of the second inverter or of a third inverter providing a first phase signal; a further sequence of inverters, an input of a first further inverter being coupled to the feedback node, and an output of another further inverter providing a second phase signal; and a control circuit for adjusting an oscillation frequency of the ring oscillator based on the relative phases of the first and second phase signals.Type: ApplicationFiled: March 31, 2016Publication date: October 6, 2016Applicant: Commissariat à I'Énergie Atomique et aux Énergies AlternativesInventors: Robert Polster, José-Luis Gonzalez Jimenez, Ivan Miro Panades
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Patent number: 9330006Abstract: A system for managing correspondence between a cache memory, subdivided into a plurality of cache areas, and a main memory, subdivided into a plurality of memory areas, includes: a mechanism allocating, to each area of the main memory, at least one area of the cache memory; a mechanism temporarily assigning, to any data row stored in one of the areas of the main memory, a cache row included only in one cache area allocated to the main memory area wherein the data row is stored; and a mechanism generating and updating settings of the allocation by activating the allocation mechanism, the temporary assigning mechanism configured to determine a cache row to be assigned to a data row based on the allocation settings.Type: GrantFiled: January 11, 2013Date of Patent: May 3, 2016Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Eric Guthmuller, Ivan Miro Panades
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Publication number: 20150046657Abstract: A system for managing correspondence between a cache memory, subdivided into a plurality of cache areas, and a main memory, subdivided into a plurality of memory areas, includes: a mechanism allocating, to each area of the main memory, at least one area of the cache memory; a mechanism temporarily assigning, to any data row stored in one of the areas of the main memory, a cache row included only in one cache area allocated to the main memory area wherein the data row is stored; and a mechanism generating and updating settings of the allocation by activating the allocation mechanism, the temporary assigning mechanism configured to determine a cache row to be assigned to a data row based on the allocation settings.Type: ApplicationFiled: January 11, 2013Publication date: February 12, 2015Applicant: Commissariat a l'energie atomique et aux ene altInventors: Eric Guthmuller, Ivan Miro Panades
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Patent number: 7725515Abstract: The present invention relates to a digital data filtering circuit. This digital data filtering circuit is able to implement the calculation steps of a discrete transform of a set of 8 original data (w), and calculating an inverse discrete transform of the set of transformed data thus obtained. For this purpose, it comprises a first filtering module (FILo1) intended to filter the odd transformed data or the 3 odd transformed data items having the highest frequencies in the set of transformed data, and a second filtering module (FILo2) connected to the first filtering module and intended to filter the 2 odd transformed data having the highest frequencies in the set of transformed data.Type: GrantFiled: July 8, 2003Date of Patent: May 25, 2010Assignee: Trident Microsystems (Far East) Ltd.Inventors: Ivan Miro Panades, Carolina Miro Sorolla
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Patent number: 7477553Abstract: A control device is provided for controlling a buffer memory that can store n data words and is capable of being used for data transfer between a first system and a second system. The control device includes a write pointer and a read pointer. The control device also includes a write management circuit and a read management circuit. The write management circuit compares the content of the write pointer and the content of the read pointer, and authorizes or does not authorize a write operation in the memory. The read management circuit compares the content of the write pointer and the content of the read pointer, and authorizes or does not authorize a read operation in the memory.Type: GrantFiled: April 13, 2007Date of Patent: January 13, 2009Assignee: STMicroelectronics SAInventor: Ivan Miro Panades