Abstract: A method of forming a semiconductor device includes providing a substrate that comprises a metal region, forming an encapsulant body of electrically insulating material on an upper surface of the metal region, forming an opening in the encapsulant body, and inserting a press-fit connector into the opening, wherein after inserting the press-fit connector into the opening, the press-fit connector is securely retained to the substrate and an interfacing end of the press-fit connector is electrically accessible.

Abstract: A package includes: at least one electronic chip; an encapsulant encapsulating at least part of the at least one electronic chip; a shielding layer on at least part of an external surface of the encapsulant; and a first heat removal body thermally coupled to the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip to a cooling fluid. The encapsulant has a surface portion that extends in a surface region extending laterally directly adjacent to the first heat removal body. The surface portion of the encapsulant delimits part of a cooling cavity configured to guide the cooling fluid. The shielding layer covers the surface portion of the encapsulant. A corresponding electronic device, method of manufacturing the package, method of manufacturing the electronic device, vehicle, and method of using the electronic device are also described.

Abstract: A molded power semiconductor package includes power semiconductor dies embedded in a mold compound and a lead frame embedded in the mold compound above the power semiconductor dies. A first part of the lead frame includes branches electrically connected to a first load terminal of the power semiconductor dies. A second part of the lead frame is spaced inward from the branches of the first part, and electrically connected to a gate terminal of the power semiconductor dies. The first part of the lead frame has a protrusion that juts out from a first side face of the mold compound to form a first lead of the molded package. A longitudinal axis of the second part of the lead frame intersects the first lead. The second part of the lead frame is physically disconnected from the first lead by a severed region of the lead frame.

Abstract: A method for fabricating a semiconductor device module includes: providing a first encapsulant layer and a core layer disposed on the first encapsulant layer, the core layer having an opening; disposing a semiconductor device in the opening, the semiconductor device having a die carrier and a semiconductor die disposed on the die carrier; dispensing an encapsulant onto the semiconductor device; applying a second polymer layer onto the encapsulant so that the encapsulant is pressed into the opening; and laminating together the first and second encapsulant layers and the encapsulant.

Abstract: A molded power semiconductor package includes: at least one first power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of first power semiconductor dies attached to the metallization layer of the at least one first power electronics carrier; at least one second power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of second power semiconductor dies attached to the metallization layer of the at least one second power electronics carrier; and a mold compound encasing the plurality of first power semiconductor dies and the plurality of second power semiconductor dies, and at least partly encasing the at least one first power electronics carrier and the at least one second power electronics carrier. The at least one first power electronics carrier and the at least one second power electronics carrier lie in a same plane.

Abstract: A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.

Abstract: A semiconductor package includes a substrate, a first and a second semiconductor die arranged on the substrate, a molded body encapsulating the first and second semiconductor dies, the molded body including a first external side facing away from the substrate, a plurality of electrical connectors extending at least partially through the molded body from the first external side to the first and/or second semiconductor die, and a plurality of plated conductive tracks arranged in trenches within the molded body on the first external side. T conductive tracks are coupled to the first and/or second semiconductor die by the electrical connectors.

Abstract: A semiconductor die package includes a semiconductor transistor die having a contact pad on an upper main face. The semiconductor die package also includes an electrical conductor disposed on the contact pad and fabricated by laser-assisted structuring of a metallic material, and an encapsulant covering the semiconductor die and at least a portion of the electrical conductor.

Abstract: A semiconductor package includes: a die carrier having a first main face and a second main face opposite to the first main face; a semiconductor die disposed on the die carrier, the semiconductor die including a first pad and a second pad; a first electrical connector disposed on the first pad; an encapsulant at least partially covering the semiconductor die, the die carrier, and the first electrical connector; and an insulation layer disposed on the second main face of the die carrier.

Abstract: A stacked module arrangement includes: a first molded electronic module; a second molded electronic module; and an interface by which the first molded electronic module and the second molded electronic module are physically and electrically connected to one another in a stacked configuration. The first molded electronic module is a power electronic module having a maximum breakdown voltage of at least 40 V and a maximum DC current of at least 10 A.

Abstract: A method for fabricating a semiconductor die package includes: providing a semiconductor transistor die, the semiconductor transistor die having a first contact pad on a first lower main face and/or a second contact pad on an upper main face; fabricating a frontside electrical conductor onto the second contact pad and a backside electrical conductor onto the first contact pad; and applying an encapsulant covering the semiconductor die and at least a portion of the electrical conductor, wherein the frontside electrical conductor and/or the backside electrical conductor is fabricated by laser-assisted structuring of a metallic structure.

Abstract: A power semiconductor module includes a leadframe having a first die pad, a second die pad separated from the first die pad, a first power lead formed as an extension of the first die pad, a second power lead separated from the first and second die pads, and a first connection region formed as an extension of the second power lead alongside the second die pad. A first plurality of power semiconductor dies is attached to the first die pad and electrically coupled in parallel. A second plurality of power semiconductor dies is attached to the second die pad and electrically coupled in parallel. A first electrical connection extends between the first plurality of power semiconductor dies and the second die pad in a first direction. A second electrical connection extends between the second plurality of power semiconductor dies and the first connection region in the first direction.

Abstract: Described are solder stop features for electronic devices. An electronic device may include an electrically insulative substrate, a metallization on the electrically insulative substrate, a metal structure attached to a first main surface of the metallization via a solder joint, and a concavity formed in a sidewall of the metallization. The concavity is adjacent at least part of the solder joint and forms a solder stop. A first section of the metal structure is spaced apart from both the metallization and solder joint in a vertical direction that is perpendicular to the first main surface of the metallization. A linear dimension of the concavity in a horizontal direction that is coplanar with the metallization is at least twice the distance by which the first section of the metal structure is spaced apart from the first main surface of the metallization in the vertical direction. Additional solder stop embodiments are described.

Abstract: An electronic device and method is disclosed. In one example, the electronic device includes an electrically insulating material, a first load electrode arranged on a first surface of the electrically insulating material, and a second load electrode arranged on a second surface of the electrically insulating material opposite to the first surface, wherein the load electrodes are separated by the electrically insulating material along the entire length on which the load electrodes have opposite sections, wherein surfaces of the load electrodes facing away from the electrically insulating material are uncovered by the electrically insulating material.

Abstract: A method of forming a semiconductor device includes providing a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, mounting one or more semiconductor dies on a portion of the structured metallization layer, forming an encapsulant body of electrically insulating material that covers the power electronics carrier and encapsulates the one or more semiconductor dies, securing a press-fit connector to the power electronics carrier with a base portion of the press-fit connector being disposed within an opening in the encapsulant body and with an interfacing end of the press-fit connector being electrically accessible from outside the encapsulant body.

Abstract: A semiconductor package includes a semiconductor die, an encapsulant body of electrically insulating material that encapsulates the semiconductor die, a thermal conduction plate comprising an outer surface that is exposed from the encapsulant body, a region of thermal interface material interposed between the thermal conduction plate and the semiconductor die, the region of thermal interface material being a liquid or semi-liquid, and a barrier that is configured to prevent the thermal interface material of the region from flowing laterally across the barrier.

Abstract: A semiconductor assembly includes a laminate substrate that includes a plurality of laminate layers of electrically insulating material stacked on top of one another, a semiconductor package that includes a package body of electrically insulating encapsulant material and a plurality of electrical contacts that are exposed from the package body, wherein the semiconductor package is embedded within the laminate layers of the laminate substrate, wherein the semiconductor package comprises a delamination mitigation feature, wherein the delamination mitigation feature comprises one or both of a macrostructure that engages with the laminate layers, and a roughened surface of microstructures that enhances adhesion between the semiconductor package and the laminate layers.

Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.

Abstract: A semiconductor package comprising a substrate, at least one semiconductor die disposed on the substrate, at least one electrical connector connected with the semiconductor die, an encapsulant covering the substrate, the at least one semiconductor die, and at least partially the electrical connector, the encapsulant comprising a recess formed into a main surface of the encapsulant, wherein the at least one electrical connector is exposed within the recess.

Abstract: A power semiconductor module includes a first substrate, wherein the first substrate includes aluminum, a first aluminum oxide layer arranged on the first substrate, a conductive layer arranged on the first aluminum oxide layer, a first semiconductor chip, wherein the first semiconductor chip is arranged on the conductive layer and is electrically connected thereto, and an electrical insulation material enclosing the first semiconductor chip, wherein the first aluminum oxide layer is configured to electrically insulate the first semiconductor chip from the first substrate.