Patents by Inventor Ivan Sanchez Esqueda

Ivan Sanchez Esqueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Physics-based reliability model for large-scale CMOS circuit design
    Patent number: 9032348
    Abstract: This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation effect(s) in a circuit simulation, a simulated defect signal level is produced. More specifically, the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and a simulated input signal level of a simulated input signal. As such, the charge degradation effect(s) are simulated externally with respect to the in silico active semiconductor component. In this manner, the in silico active semiconductor component does not need to be reprogrammed in order to simulate charge degradation effects.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: May 12, 2015
    Assignees: Arizona Board of Regents on behalf of Arizona State University, University of Southern California
    Inventors: Hugh James Barnaby, Ivan Sanchez Esqueda
  • PHYSICS-BASED RELIABILITY MODEL FOR LARGE-SCALE CMOS CIRCUIT DESIGN
    Publication number: 20140165017
    Abstract: This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation effect(s) in a circuit simulation, a simulated defect signal level is produced. More specifically, the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and a simulated input signal level of a simulated input signal. As such, the charge degradation effect(s) are simulated externally with respect to the in silico active semiconductor component. In this manner, the in silico active semiconductor component does not need to be reprogrammed in order to simulate charge degradation effects.
    Type: Application
    Filed: December 9, 2013
    Publication date: June 12, 2014
    Applicants: Arizona State University
    Inventors: Hugh James Barnaby, Ivan Sanchez Esqueda