Abstract: A system, including at least one central processing unit, at least one memory unit, and a plurality of integrated circuits that form a switching fabric configured to propagate data packets between the at least one central processing unit and the at least one memory unit, wherein the switching fabric is constructed using at least two directed acyclic graph (DAG) networks.

Abstract: One embodiment of the present invention provides a system that electronically aligns mini-bars on different semiconductor chips which are situated face-to-face to facilitate communication between the semiconductor chips through capacitive coupling. During operation, the system measures an alignment between a first chip and a second chip. The system then selects a group of transmitter mini-bars on the first chip to form a transmitter bit position based on the measured alignment. In this way, the system allows a data signal to be distributed to and transmitted by the mini-bars that form the transmitter bit position. The system also selects a group of receiver mini-bars on the second chip to form a receiver bit position based on the measured alignment. Next, the system associates transmitter bit positions on the first chip with proximate receiver bit positions on the second chip based on the measured alignment.

Abstract: One embodiment of the present invention provides a capacitively-coupled receiver amplifier that has an input with no DC coupling. A DC voltage is programmed on the input. During programming, a transmitter is held at a voltage at a midpoint between a voltage that represents a logical “1” and a voltage that represents a logical “0” and the input voltage of the receiver amplifier is programmed to be substantially the switching-threshold voltage for the receiver amplifier. Then, during normal data communication, the transmitter drives high and low electrical signals that are coupled to the receiver amplifier. Since the input of the receiver amplifier has been substantially set to the DC voltage, the receiver amplifier need not control the DC voltage of the input for each transition in the electrical signals.

Abstract: One embodiment of the present invention provides a system that facilitates capacitive inter-chip communication. During operation, the system first determines an alignment between a first semiconductor die and a second semiconductor die. Next, electrical signals are selectively routed to at least one interconnect pad in a plurality of interconnect pads based on the alignment thereby facilitating communication between the first semiconductor die and the second semiconductor die. The plurality of interconnect pads can include transmitting pads, receiving pads, and transmitting and receiving pads. The alignment may be determined continuously or at times separated by an interval, where the interval is fixed or variable. Several variations on this embodiment are provided.

Abstract: An apparatus and method for finding suitable transistor sizes for complex logic networks. An electrical “logical effort model” of a logic circuit is made by replacing each logic element with a simple electrical model and retaining the wiring topology of the original circuit. The logical effort model is a DC circuit with parameters that depending only on the gain chosen for the logic elements in the critical path, the stray capacitance of critical connections, and the logical effort of each logic element. A circuit simulation of the logical effort model produces voltages proportional to desired transistor widths. In working on the electrical model, the circuit simulator merely solves the set of simultaneous equations implied by the model. Alternate methods are also described.